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programmable-logic:cora-z7:start [2021/05/14 23:04] – ↷ Page moved from reference:programmable-logic:cora-z7:start to programmable-logic:cora-z7:start Arthur Brownprogrammable-logic:cora-z7:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Cora Z7 ====== ====== Cora Z7 ======
 {{Digilent Infobox {{Digilent Infobox
-| Store Page = https://store.digilentinc.com/cora-z7/+| Store Page = https://digilent.com/shop/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/
 | Manual = [[reference-manual]] | Manual = [[reference-manual]]
 | Support = http://forum.digilentinc.com | Support = http://forum.digilentinc.com
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 | Bullet = Programmable from JTAG and microSD card  | Bullet = Programmable from JTAG and microSD card 
 | Header = Key FPGA Specifications | Header = Key FPGA Specifications
-| Part Number = XC7Z010-1CLG400 \\ (XC7Z007S-1CLG400*) +| Part Number = XC7Z007S-1CLG400 \\ (XC7Z010-1CLG400*) 
-| Logic Slices = 4,400 (3,600*) +| Logic Slices = 3,600 (4,400*) 
-| 6-input LUTs =  17,600 (14,400*) +| 6-input LUTs =  14,400 (17,600*) 
-| Flip-Flops = 35,200 (28,800*) +| Flip-Flops = 28,800 (35,200*) 
-| Block RAM = 270 KB (225 KB*) +| Block RAM = 225 KB (270 KB*) 
-| DSP Slices = 80 (66*)+| DSP Slices = 66 (80*)
 | Clock Resources = Zynq PLL with 4 outputs \\ 2 PLLs \\ 2 MMCMs \\ 125 MHz external clock | Clock Resources = Zynq PLL with 4 outputs \\ 2 PLLs \\ 2 MMCMs \\ 125 MHz external clock
 | Internal ADC = Dual-channel, 1 MSPS | Internal ADC = Dual-channel, 1 MSPS
-| Bullet = (*Z7-07S variant value in parentheses where different)+| Bullet = (*Z7-10 variant value in parentheses where different)
 | Header = Connectivity and On-board I/O | Header = Connectivity and On-board I/O
 | USB = USB-UART \\ USB-JTAG Programmer \\ USB Host | USB = USB-UART \\ USB-JTAG Programmer \\ USB Host
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 ---- ----
 ===== Tutorials ===== ===== Tutorials =====
-{{topic>cora-z7 +tutorial -legacy -in-work}}+ 
 +  * [[programmable-logic:guides:installing-vivado-and-vitis]] 
 +    * Walks through installing Vivado and Vitis, the development environments used to create hardware and software applications targeting Digilent FPGA development boards. 
 +  * [[programmable-logic:guides:getting-started-with-ipi]] 
 +    * Walks through using Vivado and Vitis to create a design in hardware and software that uses a processor to control buttons and LEDs. 
 +  * [[programmable-logic:guides:getting-started-with-vivado]] 
 +    * Walks through using Vivado to create a simple design that blinks a single LED. 
 +  * [[learn/programmable-logic/tutorials/pmod-ips/start]] 
 +    * Digilent Pmod IPs can be used to control connected Pmods from baremetal software. 
 +    * It should be noted that not all Pmods are supported and that Pmod IPs are only supported in versions of Vivado 2019.1 and older.
  
 ---- ----
 ===== Example Projects ===== ===== Example Projects =====
-{{topic>cora-z7 +project -legacy}}+ 
 +=== Demos Supporting Vivado and Vitis 2020.1 === 
 +  * [[./demos/pmod-vga]] 
 +  * [[./demos/basic-io]] 
 +  * [[./demos/xadc]] 
 +=== Other Demos === 
 +  * [[pmod/pmodi2s2/fpga-demo]]
  
 ---- ----
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 ---- ----
  
-{{tag>programmable-logic programmable-logic-start cora-z7 resource-center}}+{{tag>programmable-logic cora-z7 resource-center}}