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programmable-logic:cora-z7:reference-manual [2021/09/29 20:15] – Arthur Brownprogrammable-logic:cora-z7:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Cora Z7 Reference Manual ====== ====== Cora Z7 Reference Manual ======
 +
 +<WRAP round important>
 +The Cora Z7-10 variant is no longer in production. Once the current stock is depleted, it will be discontinued. The Cora Z7-07S will not be affected and will remain in production. 
 +</WRAP>
 +
 The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000 All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz ARM Cortex-A9 processor with a Xilinx 7-series FPGA. This pairing grants the ability to surround the processor with a unique set of software defined peripherals and controllers, tailored for the target application. The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000 All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz ARM Cortex-A9 processor with a Xilinx 7-series FPGA. This pairing grants the ability to surround the processor with a unique set of software defined peripherals and controllers, tailored for the target application.
  
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   * **ZYNQ Processor**   * **ZYNQ Processor**
-    * 667MHz dual-core (*single-core) Cortex-A9 processor+    * 667MHz single-core (*dual-core) Cortex-A9 processor
     * FPGA Programmable logic equivalent to Artix-7 FPGA     * FPGA Programmable logic equivalent to Artix-7 FPGA
-      * 4,400 Programmable logic slices (*3,600) +      * 3,600 Programmable logic slices (*4,400) 
-      * 80 DSP slices (*60) +      * 60 DSP slices (*80) 
-      * 270 KB of block RAM (*225 KB)+      * 225 KB of block RAM (*270 KB)
     * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports     * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
     * High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO     * High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
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       * 12 additional FPGA Digital I/O       * 12 additional FPGA Digital I/O
  
-(*Z7-07S variant in parentheses where different)+(*Z7-10 variant in parentheses where different)
  
 {{ reference:programmable-logic:cora-z7:cora-z7-callout.png?800 |}} {{ reference:programmable-logic:cora-z7:cora-z7-callout.png?800 |}}
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 ====== Purchasing Options and Board Variants ====== ====== Purchasing Options and Board Variants ======
  
-The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.+A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
  
 The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below: The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below:
  
-^ Product Variant          ^ Cora Z7-10           ^ Cora Z7-07S          ^ +^ Product Variant          ^ Cora Z7-07S          ^ Cora Z7-10 (No longer in production)  ^ 
-^ Zynq Part                | XC7Z010-1CLG400C     | XC7Z007S-1CLG400C    | +^ Zynq Part                | XC7Z007S-1CLG400C    | XC7Z010-1CLG400C                      | 
-^ ARM Processor Cores      | 2                    | 1                    | +^ ARM Processor Cores      | 1                    | 2                                     | 
-^ 1 MSPS On-chip ADC       | Yes                  | Yes                  | +^ 1 MSPS On-chip ADC       | Yes                  | Yes                                   | 
-^ Look-up Tables (LUTs)    | 17,600               | 14,400               | +^ Look-up Tables (LUTs)    | 14,400               | 17,600                                | 
-^ Flip-Flops               | 35,200               | 28,800               | +^ Flip-Flops               | 28,800               | 35,200                                | 
-^ DSP Slices               | 80                   | 66                   | +^ DSP Slices               | 66                   | 80                                    | 
-^ Block RAM                | 270 KB               | 225 KB               | +^ Block RAM                | 225 KB               | 270 KB                                | 
-^ Clock Management Tiles   | 2                    | 2                    | +^ Clock Management Tiles   | 2                    | 2                                     |
-/* +
-FIXME Optional 5 Volt 4 Amp Power Supply+
  
-FIXME Optional Micro USB Cable. 
- 
-FIXME Optional microSD Card with Out-of-Box Demonstration Project. 
-*/ 
 For more information on purchasing, see the [[https://digilent.com/shop/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/|Cora Z7 Product Page]]. For more information on purchasing, see the [[https://digilent.com/shop/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/|Cora Z7 Product Page]].
  
 +/*
 **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[programmable-logic:arty-z7:start|Arty Z7-20]] //if they are interested in these types of applications.// **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[programmable-logic:arty-z7:start|Arty Z7-20]] //if they are interested in these types of applications.//
 +*/
  
 ---- ----
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 Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the [[start|Cora Z7 Resource Center]]. Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the [[start|Cora Z7 Resource Center]].
  
-Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https://forum.digilentinc.com|Digilent Forum]].+/* Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https://forum.digilentinc.com|Digilent Forum]]. */
  
 ---- ----
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 The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]]. 
  
 Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals.  Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. 
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 **Stage 2**  **Stage 2** 
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools.
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design.  Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design. 
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 ===== 6 microSD Slot ===== ===== 6 microSD Slot =====
  
-The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.+The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
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 Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended.  Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended. 
  
-Refer to section 3.1, [[#microsd-boot-mode|microSD Boot Mode]], for information on how to boot the Cora Z7 from an SD card. For more information, consult the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+Refer to section 3.1, [[#microsd-boot-mode|microSD Boot Mode]], for information on how to boot the Cora Z7 from an SD card. For more information, consult the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/64™ compatible identifier. On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/64™ compatible identifier.
  
-For more information on using the Gigabit Ethernet MAC, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more information on using the Gigabit Ethernet MAC, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 ===== 10 Reset Sources ===== ===== 10 Reset Sources =====
  
-==== 10.1 Power-on Reset ====+==== 10.1 Power-on Reset Signals ====
  
 The Zynq Processing System (PS) supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Cora Z7 drives this signal from the nRESET signal of the DA9062 DC-DC converter system in order to hold the system in reset until all power supplies are valid. A push-button, labeled RESET, can be used to toggle the power-on reset signal. The Zynq Processing System (PS) supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Cora Z7 drives this signal from the nRESET signal of the DA9062 DC-DC converter system in order to hold the system in reset until all power supplies are valid. A push-button, labeled RESET, can be used to toggle the power-on reset signal.
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 //Table 13.1.1. Shield Voltage Specifications// //Table 13.1.1. Shield Voltage Specifications//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf|Zynq-7000 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds190-Zynq-7000-Overview|Zynq-7000 datasheet]] from Xilinx.
  
 The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind. The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind.
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 Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^
-| Cora Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |+| Cora Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: [[https://support.xilinx.com/s/article/53039]]. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |
  
 {{tag>rm doc cora-z7}} {{tag>rm doc cora-z7}}