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programmable-logic:cmod-s7:reference-manual [2021/05/14 16:04] – ↷ Page moved from reference:programmable-logic:cmod-s7:reference-manual to programmable-logic:cmod-s7:reference-manual Arthur Brownprogrammable-logic:cmod-s7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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       * 2 power pins       * 2 power pins
  
-{{ cmod-s7-callout.png |}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-callout.png |}}
  
 ^ Callout  ^ Description                    ^ Callout  ^ Description                ^ ^ Callout  ^ Description                    ^ Callout  ^ Description                ^
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 The Cmod S7 is fully compatible with the high-performance Vivado ® Design Suite versions 2018.1 and newer. It is supported under the free WebPACK™ installation option, which does not require a license, so designs can be implemented at no additional cost. This free installation includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the [[start|Cmod S7 Resource Center]]. The Cmod S7 is fully compatible with the high-performance Vivado ® Design Suite versions 2018.1 and newer. It is supported under the free WebPACK™ installation option, which does not require a license, so designs can be implemented at no additional cost. This free installation includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the [[start|Cmod S7 Resource Center]].
  
-The Cmod S7 can be used with Vivado 2017.4, but WebPACK installations of this version of Vivado may not contain the device files for the specific Spartan-7 FPGA used on the Cmod S7. See this [[https://www.xilinx.com/support/answers/70505.html|Xilinx Answer Record]] for more information, and for a solution.+The Cmod S7 can be used with Vivado 2017.4, but WebPACK installations of this version of Vivado may not contain the device files for the specific Spartan-7 FPGA used on the Cmod S7. See this [[https://support.xilinx.com/s/article/70505|Xilinx Answer Record]] for more information, and for a solution.
  
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 The Cmod S7 uses a Linear Technologies LTC3569 triple output buck power regulator to generate the needed voltages for the onboard components. It is connected as shown in Figure 1.1. The characteristics of the outputs are shown in Table 1.1. The Cmod S7 uses a Linear Technologies LTC3569 triple output buck power regulator to generate the needed voltages for the onboard components. It is connected as shown in Figure 1.1. The characteristics of the outputs are shown in Table 1.1.
  
-{{ cmod-s7-power.png?700 |Figure 1.1 Power Supply}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-power.png?700 |Figure 1.1 Power Supply}}
  
 //Figure 1.1 Power Supply// //Figure 1.1 Power Supply//
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 Figure 2.1 shows the different options available for configuring the FPGA.  Figure 2.1 shows the different options available for configuring the FPGA. 
  
-{{ cmod-s7-config.png?700 |Figure 2.1 Configuration}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-config.png?700 |Figure 2.1 Configuration}}
  
 //Figure 2.1 Configuration// //Figure 2.1 Configuration//
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 The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J5). JTAG programming can be performed any time after the Cmod S7 has been powered on. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transferred over JTAG. The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J5). JTAG programming can be performed any time after the Cmod S7 has been powered on. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transferred over JTAG.
  
-Programming the Cmod S7 with an uncompressed bitstream using the onboard USB-JTAG circuitry usually takes around FIXME seconds. JTAG programming can be performed by Vivado's Hardware Manager.+Programming the Cmod S7 with an uncompressed bitstream using the onboard USB-JTAG circuitry usually takes around 6 seconds. JTAG programming can be performed by Vivado's Hardware Manager.
  
 ==== 2.2 Quad-SPI Configuration ==== ==== 2.2 Quad-SPI Configuration ====
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 FPGA Configuration files can be written to the Quad-SPI Flash (Macronix part number MX25L3233F). The FPGA will automatically read a configuration file from this device at power on. A Spartan-7 25T configuration file requires 9,935,224 bits of memory, leaving about 69% of the flash device (or ~2.8 MB) available for user data. A common use for this extra memory is to store MicroBlaze programs too big to fit in the onboard block memory. These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into the bitstream, and then program the bitstream and large MicroBlaze program into the Quad SPI Flash using Xilinx SDK. FPGA Configuration files can be written to the Quad-SPI Flash (Macronix part number MX25L3233F). The FPGA will automatically read a configuration file from this device at power on. A Spartan-7 25T configuration file requires 9,935,224 bits of memory, leaving about 69% of the flash device (or ~2.8 MB) available for user data. A common use for this extra memory is to store MicroBlaze programs too big to fit in the onboard block memory. These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into the bitstream, and then program the bitstream and large MicroBlaze program into the Quad SPI Flash using Xilinx SDK.
  
-The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI IP core can be used to read/write the flash in a MicroBlaze design. Refer to [[https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf|Xilinx's product guide]] for this core to learn more about using it, or to [[http://www.macronix.com/Lists/Datasheet/Attachments/6744/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf|Macronix's datasheet]] for the flash device to learn how to implement a custom controller. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O.+The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI IP core can be used to read/write the flash in a MicroBlaze design. Refer to [[https://docs.xilinx.com/v/u/en-US/pg153-axi-quad-spi|Xilinx's product guide]] for this core to learn more about using it, or to [[http://www.macronix.com/Lists/Datasheet/Attachments/6744/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf|Macronix's datasheet]] for the flash device to learn how to implement a custom controller. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O.
  
-{{ cmod-s7-flash.png?400 |Figure 3.1 Flash Interface}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-flash.png?400 |Figure 3.1 Flash Interface}}
  
 //Figure 3.1 Flash Interface// //Figure 3.1 Flash Interface//
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 ===== 4 Oscillators/Clocks ===== ===== 4 Oscillators/Clocks =====
  
-The Cmod S7 includes a 12 MHz crystal oscillator connected to pin M9 (an MRCC input on bank 14). This clock is intended to be used as a general purpose system clock. The clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. The 12 MHz input clock cannot directly drive a PLL because they have a minimum input frequency of 19 MHz. Some rules restrict which MMCMs and PLLs may be driven by the 12 MHz input clock. For a full description of these rules and of the capabilities of the Spartan-7 clocking resources, refer to [[https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf|Xilinx UG472]], titled “7 Series FPGAs Clocking Resources User Guide”.+The Cmod S7 includes a 12 MHz crystal oscillator connected to pin M9 (an MRCC input on bank 14). This clock is intended to be used as a general purpose system clock. The clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. The 12 MHz input clock cannot directly drive a PLL because they have a minimum input frequency of 19 MHz. Some rules restrict which MMCMs and PLLs may be driven by the 12 MHz input clock. For a full description of these rules and of the capabilities of the Spartan-7 clocking resources, refer to [[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking|Xilinx UG472]], titled “7 Series FPGAs Clocking Resources User Guide”.
  
 Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
  
-{{ cmod-s7-clocking.png?400 |Figure 4.1 Clock Input}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-clocking.png?400 |Figure 4.1 Clock Input}}
  
 //Figure 4.1 Clock Input// //Figure 4.1 Clock Input//
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 The connections between the FT2232HQ and the Spartan-7 are shown in Figure 5.1. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case, a PC connected to the Micro USB port. The connections between the FT2232HQ and the Spartan-7 are shown in Figure 5.1. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case, a PC connected to the Micro USB port.
  
-{{ cmod-s7-usbuart.png?600 |Figure 5.1 USB-UART Bridge}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-usbuart.png?600 |Figure 5.1 USB-UART Bridge}}
  
 //Figure 5.1 USB-UART Bridge// //Figure 5.1 USB-UART Bridge//
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 Figure 6.1 shows how each of the LEDs and push buttons are connected to the Spartan-7. Figure 6.1 shows how each of the LEDs and push buttons are connected to the Spartan-7.
  
-{{ cmod-s7-basic-io.png?600 |Figure 5.1 Cmod S7 Basic I/O}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-basic-io.png?600 |Figure 5.1 Cmod S7 Basic I/O}}
  
 //Figure 6.1 Cmod S7 Basic I/O// //Figure 6.1 Cmod S7 Basic I/O//
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 The Cmod S7 has a 48-pin DIP form factor connector, implemented as four 9-pin headers for connecting to breadboards and custom fixtures. The pins have 100 mil spacing, and the entire module is 0.7 inches by 3.05 inches. Headers J1 and J3 are separated by 700 mil lengthwise along the Cmod, measured from the center of the innermost pins, as are headers J2 and J4. Headers J1 and J2 are separated by 600 mil across the board, as are headers J3 and J4. Of the 48 possible pin locations, 36 are populated on the four headers. Of these, 32 are directly connected to FPGA Digital I/Os, 2 are voltage-divided and connected to FPGA analog inputs, and two are connected to power pins. The pin and header numbers are shown in Figure 7.1. The Cmod S7 has a 48-pin DIP form factor connector, implemented as four 9-pin headers for connecting to breadboards and custom fixtures. The pins have 100 mil spacing, and the entire module is 0.7 inches by 3.05 inches. Headers J1 and J3 are separated by 700 mil lengthwise along the Cmod, measured from the center of the innermost pins, as are headers J2 and J4. Headers J1 and J2 are separated by 600 mil across the board, as are headers J3 and J4. Of the 48 possible pin locations, 36 are populated on the four headers. Of these, 32 are directly connected to FPGA Digital I/Os, 2 are voltage-divided and connected to FPGA analog inputs, and two are connected to power pins. The pin and header numbers are shown in Figure 7.1.
  
-{{ cmod-s7-dip.png?400 |Figure 7.1 DIP Pin Diagram}}+{{ reference:programmable-logic:cmod-s7:cmod-s7-dip.png?400 |Figure 7.1 DIP Pin Diagram}}
  
 //Figure 7.1 DIP Pin Diagram// //Figure 7.1 DIP Pin Diagram//
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 The pins directly connected to the FPGA can be used as general purpose inputs or outputs. Each of these pins is connected to the FPGA via a 240 Ohm series resistor. The series resistors prevent short circuits that can occur if a user accidentally drives a signal that is supposed to be used as an input. The downside to this added protection is that these resistors limit the maximum switching speed of these signals to 25 MHz. These pins support input voltages of up to 3.5V. The pins directly connected to the FPGA can be used as general purpose inputs or outputs. Each of these pins is connected to the FPGA via a 240 Ohm series resistor. The series resistors prevent short circuits that can occur if a user accidentally drives a signal that is supposed to be used as an input. The downside to this added protection is that these resistors limit the maximum switching speed of these signals to 25 MHz. These pins support input voltages of up to 3.5V.
  
-For more information on the electrical characteristics of these pins, please see Xilinx's [[https://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf|Spartan-7 Datasheet]].+For more information on the electrical characteristics of these pins, please see Xilinx's [[https://docs.xilinx.com/v/u/en-US/ds189-spartan-7-data-sheet|Spartan-7 Datasheet]].
  
 ==== 7.2 Analog Inputs ==== ==== 7.2 Analog Inputs ====
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 //Figure 7.2.1 Analog Input Circuit// //Figure 7.2.1 Analog Input Circuit//
  
-The XADC core within the Spartan-7 is a dual-channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by either of the two auxiliary analog inputs to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration port (DRP). The DRP also provides access to a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to [[https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf|Xilinx UG480]], titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". A demo that uses the XADC core is available on the [[start|Cmod S7 Resource Center]]+The XADC core within the Spartan-7 is a dual-channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by either of the two auxiliary analog inputs to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration port (DRP). The DRP also provides access to a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to [[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC|Xilinx UG480]], titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". A demo that uses the XADC core is available on the [[start|Cmod S7 Resource Center]]
  
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