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| programmable-logic:cmod-a7:reference-manual [2022/03/24 23:48] – [Features] add production notice to purchasing options table Arthur Brown | programmable-logic:cmod-a7:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| //Table 8.1. DIP Pin Voltage Ratings// | //Table 8.1. DIP Pin Voltage Ratings// | ||
| - | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/ | + | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/ |
| ==== 8.2 Analog Inputs ==== | ==== 8.2 Analog Inputs ==== | ||
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| //Figure 8.2.1. Analog Input Circuit// | //Figure 8.2.1. Analog Input Circuit// | ||
| - | The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[http://www.xilinx.com/ | + | The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[https://docs.xilinx.com/ |
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