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programmable-logic:cmod-a7:reference-manual [2022/03/11 18:04] – Marthaprogrammable-logic:cmod-a7:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 The only difference between the Cmod A7-15T and Cmod A7-35T are the capabilities of the FPGA found on the board. They compare as follows: The only difference between the Cmod A7-15T and Cmod A7-35T are the capabilities of the FPGA found on the board. They compare as follows:
  
-^ Product Variant          ^ Cmod A7-15T          ^ Cmod A7-35T          ^ +^ Product Variant          ^ Cmod A7-35T          ^ Cmod A7-15T (No longer in production)  ^ 
-^ FPGA Part                | XC7A15T-1CPG236C     | XC7A35T-1CPG236C     |+^ FPGA Part                | XC7A35T-1CPG236C     | XC7A15T-1CPG236C     |
 ^ 1 MSPS On-chip ADC       | Yes                  | Yes                  | ^ 1 MSPS On-chip ADC       | Yes                  | Yes                  |
 ^ Programming options      | Quad-SPI Flash/JTAG  | Quad-SPI Flash/JTAG  | ^ Programming options      | Quad-SPI Flash/JTAG  | Quad-SPI Flash/JTAG  |
-^ Look-up Tables (LUTs)    | 10,400               | 20,800               | +^ Look-up Tables (LUTs)    | 20,800               | 10,400               | 
-^ Flip-Flops               | 20,800               | 41,600               | +^ Flip-Flops               | 41,600               | 20,800               | 
-^ Block RAM                | 112.5 KB             | 225 KB               |+^ Block RAM                | 225 KB               | 112.5 KB             |
 ^ Clock Management Tiles   | 5                    | 5                    | ^ Clock Management Tiles   | 5                    | 5                    |
  
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 //Table 8.1. DIP Pin Voltage Ratings// //Table 8.1. DIP Pin Voltage Ratings//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix 7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/iAkxxTOk96ANLJqYf2hgrQ|Artix 7 datasheet]] from Xilinx.
  
 ==== 8.2 Analog Inputs ==== ==== 8.2 Analog Inputs ====
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 //Figure 8.2.1. Analog Input Circuit// //Figure 8.2.1. Analog Input Circuit//
  
-The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf|7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter]]. A demo that uses the XADC core is available on the Cmod A7 resource center.+The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC|7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter]]. A demo that uses the XADC core is available on the Cmod A7 resource center.
  
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