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programmable-logic:basys-3:start [2022/03/04 20:23] – Update tutorials links Arthur Brownprogrammable-logic:basys-3:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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   * [[programmable-logic:guides:getting-started-with-vivado]]   * [[programmable-logic:guides:getting-started-with-vivado]]
     * Walks through using Vivado to create a simple design that blinks a single LED.     * Walks through using Vivado to create a simple design that blinks a single LED.
-  * [[learn/programmable-logic/tutorials/pmod-ips/2018.2]]+  * [[learn/programmable-logic/tutorials/pmod-ips/start]]
     * Digilent Pmod IPs can be used to control connected Pmods from baremetal software.     * Digilent Pmod IPs can be used to control connected Pmods from baremetal software.
-    * It should be noted that not all Pmods are supported and that Pmod IPs are only supported in versions of Vivado 2019.1 and newer.+    * It should be noted that not all Pmods are supported and that Pmod IPs are only supported in versions of Vivado 2019.1 and older.
  
   * [[/learn/programmable-logic/tutorials/basys-3-programming-guide/start]]   * [[/learn/programmable-logic/tutorials/basys-3-programming-guide/start]]
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 ---- ----
 ===== Example Projects ===== ===== Example Projects =====
-{{topic>basys-3 +project -legacy}}+**Note:** //The latest version of Vivado supported by these projects is 2020.1.// 
 + 
 +  * [[./demos/abacus]] 
 +  * [[./demos/gpio]] 
 +  * [[./demos/keyboard]] 
 +  * [[./demos/xadc]]
  
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   * {{:reference:programmable-logic:basys-3:basys_3_dimensions.zip| Basys3 Mechanical Drawing }}   * {{:reference:programmable-logic:basys-3:basys_3_dimensions.zip| Basys3 Mechanical Drawing }}
   * [[https://www.mhprofessional.com/9781259837906-usa-digital-system-design-with-fpga-implementation-using-verilog-and-vhdl-group | Digital System Design With FPGA: Implementation Using Verilog And VHDL]]   * [[https://www.mhprofessional.com/9781259837906-usa-digital-system-design-with-fpga-implementation-using-verilog-and-vhdl-group | Digital System Design With FPGA: Implementation Using Verilog And VHDL]]
 +  * [[learn/programmable-logic/tutorials/use-flip-flops-to-build-a-clock-divider/start]]
  
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 {{tag>programmable-logic programmable-logic-start basys-3 resource-center}} {{tag>programmable-logic programmable-logic-start basys-3 resource-center}}