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programmable-logic:arty:reference-manual [2021/05/14 16:06] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:arty:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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     * Arduino/ChipKit Shield connector     * Arduino/ChipKit Shield connector
  
-Arty is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Arty Resource Center, accessible from reference.digilentinc.com.+Arty is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the [[start|Arty Resource Center]].
  
 {{ :arty:labelled_photo.png |Arty board with callouts.}} {{ :arty:labelled_photo.png |Arty board with callouts.}}
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 Two LEDs found in the Ethernet connector (J9) are connected to the PHY to provide link status and data activity feedback. See the PHY datasheet for details. Note that it is normal for one LED to be illuminated and one to be off, even when not using the Ethernet PHY. Two LEDs found in the Ethernet connector (J9) are connected to the PHY to provide link status and data activity feedback. See the PHY datasheet for details. Note that it is normal for one LED to be illuminated and one to be off, even when not using the Ethernet PHY.
  
-Vivado IPI based designs can access the PHY using either the AXI EthernetLite IP core, the AXI 1G/2.5G Ethernet Subsystem IP core, or the Tri Mode Ethernet MAC IP core. A 25 MHz clock needs to be generated for the X1 pin of the external PHY, labeled ETH_REF_CLK in the Arty schematic. To learn how to properly use the Ethernet PHY in a Microblaze design on the Arty, refer to the Getting Started with Microblaze Servers tutorial on the Arty Resource Center at reference.digilentinc.com/arty.+Vivado IPI based designs can access the PHY using either the AXI EthernetLite IP core, the AXI 1G/2.5G Ethernet Subsystem IP core, or the Tri Mode Ethernet MAC IP core. A 25 MHz clock needs to be generated for the X1 pin of the external PHY, labeled ETH_REF_CLK in the Arty schematic. To learn how to properly use the Ethernet PHY in a Microblaze design on the Arty, refer to the Getting Started with Microblaze Servers tutorial on the [[start|Arty Resource Center]].
  
 For further information on the Ethernet PHY, refer to the DP83848J data sheet. For further information on the Ethernet PHY, refer to the DP83848J data sheet.
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 ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    | ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    |
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet|Artix-7 datasheet]] from Xilinx.
  
 ==== 11.2 Shield Analog I/O ==== ==== 11.2 Shield Analog I/O ====