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programmable-logic:arty-z7:reference-manual [2021/05/14 23:03] – ↷ Page moved from reference:programmable-logic:arty-z7:reference-manual to programmable-logic:arty-z7:reference-manual Arthur Brownprogrammable-logic:arty-z7:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 On the Arty Z7-10, the inner row of the digital shield (IO26-IO41) and IOA (also referred to as IO42) are not connected to the FPGA, and A0-A5 can only be used as analog inputs. This will not affect the functionality of most existing Arduino shields, because most do not use this inner row of digital signals. On the Arty Z7-10, the inner row of the digital shield (IO26-IO41) and IOA (also referred to as IO42) are not connected to the FPGA, and A0-A5 can only be used as analog inputs. This will not affect the functionality of most existing Arduino shields, because most do not use this inner row of digital signals.
  
-The board can be purchased stand-alone or with a voucher to unlock the Xilinx SDSoC toolset. The SDSoC voucher unlocks a 1 year license and can only be used with the Arty Z7. After the license expires, any version of SDSoC that was released during this 1 year period can continue to be used indefinitely. For more information on purchasing, see the [[http://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/|Arty Z7 Product Page]]. At the time of purchase, it is also possible to add-on a microSD card, 12V 3A power supply, and micro USB cable as needed. +The board can be purchased stand-alone or with a voucher to unlock the Xilinx SDSoC toolset. The SDSoC voucher unlocks a 1 year license and can only be used with the Arty Z7. After the license expires, any version of SDSoC that was released during this 1 year period can continue to be used indefinitely. For more information on purchasing, see the [[https://digilent.com/shop/arty-z7-zynq-7000-soc-development-board/|Arty Z7 Product Page]]. At the time of purchase, it is also possible to add-on a microSD card, 12V 3A power supply, and micro USB cable as needed. 
  
 Note that due to the smaller FPGA in the Zynq-7010, it is not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the Arty Z7-20 if they are interested in these types of applications. Note that due to the smaller FPGA in the Zynq-7010, it is not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the Arty Z7-20 if they are interested in these types of applications.
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 The Arty Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Arty Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL.  The Arty Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Arty Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. 
  
-Zynq platforms are well-suited to be embedded Linux targets, and Arty Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the [[reference:programmable-logic:arty-z7:start|Arty Z7 Resource Center]].+Zynq platforms are well-suited to be embedded Linux targets, and Arty Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]].
  
 The Arty Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a Video capable platform with Linux support in time for the SDSoC 2017.1 release. Note that due to the smaller FPGA in the Arty Z7-10, only very basic video processing demos are included with that platform. Digilent recommends the Arty Z7-20 for those interested in video processing. The Arty Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a Video capable platform with Linux support in time for the SDSoC 2017.1 release. Note that due to the smaller FPGA in the Arty Z7-10, only very basic video processing demos are included with that platform. Digilent recommends the Arty Z7-20 for those interested in video processing.
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 The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]]. 
  
-Table 2.1 depicts the external components connected to the MIO pins of the Arty Z7. The Zynq Presets File found on the [[reference:programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. +Table 2.1 depicts the external components connected to the MIO pins of the Arty Z7. The Zynq Presets File found on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. 
  
 |  **MIO 500 3.3 V**  |  **Peripherals**                                                                ||||| |  **MIO 500 3.3 V**  |  **Peripherals**                                                                |||||
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 **Stage 2**  **Stage 2** 
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
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 The Arty Z7 supports three different boot modes: microSD, Quad SPI Flash, and JTAG. The boot mode is selected using the Mode jumper (JP4), which affects the state of the Zynq configuration pins after power-on. Figure 3.1 depicts how the Zynq configuration pins are connected on the Arty Z7. The Arty Z7 supports three different boot modes: microSD, Quad SPI Flash, and JTAG. The boot mode is selected using the Mode jumper (JP4), which affects the state of the Zynq configuration pins after power-on. Figure 3.1 depicts how the Zynq configuration pins are connected on the Arty Z7.
  
-{{ arty-z7-config.png?600 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-config.png?600 |}}
  
 //Figure 3.1. Arty Z7 configuration pins.// //Figure 3.1. Arty Z7 configuration pins.//
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   * Powered from 3.3V    * Powered from 3.3V 
  
-The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad SPI clock frequency greater than FQSPICLK2 (See the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]] for more on this). +The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad SPI clock frequency greater than FQSPICLK2 (See the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]] for more on this). 
  
 In manufacturing, parts sometimes need to be replaced when the product goes end-of-life. The Quad SPI Flash memory on any particular Arty Z7 may be one of the drop-in replacements found in the Table 4.1 below. To determine which part is used by a particular board, look at the part number printed on IC19 on the bottom of the Arty Z7 (See Figure 4.1). In manufacturing, parts sometimes need to be replaced when the product goes end-of-life. The Quad SPI Flash memory on any particular Arty Z7 may be one of the drop-in replacements found in the Table 4.1 below. To determine which part is used by a particular board, look at the part number printed on IC19 on the bottom of the Arty Z7 (See Figure 4.1).
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 Both the memory chips and the PS DDR bank are powered from the 1.5V supply. The mid-point reference of 0.75V is created with a simple resistor divider and is available to the Zynq as external reference. Both the memory chips and the PS DDR bank are powered from the 1.5V supply. The mid-point reference of 0.75V is created with a simple resistor divider and is available to the Zynq as external reference.
  
-For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays. For your convenience, the Zynq presets file for the Arty Z7 is provided on the [[reference:programmable-logic:arty-z7:start|resource center]] and automatically configures the Zynq Processing System IP core with the correct parameters.+For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays. For your convenience, the Zynq presets file for the Arty Z7 is provided on the [[programmable-logic:arty-z7:start|resource center]] and automatically configures the Zynq Processing System IP core with the correct parameters.
  
 For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read data eye options in the PS Configuration Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays, process variations and thermal drift. Optimum starting values for the training process are the board delays (propagation delays) for certain memory signals.  For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read data eye options in the PS Configuration Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays, process variations and thermal drift. Optimum starting values for the training process are the board delays (propagation delays) for certain memory signals. 
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Arty Z7 memory interface PCB design.  Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Arty Z7 memory interface PCB design. 
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ¹Maximum actual clock frequency is 525 MHz on the Arty Z7 due to PLL limitation. ¹Maximum actual clock frequency is 525 MHz on the Arty Z7 due to PLL limitation.
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 The Arty Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J14) that lets you use PC applications to communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller. The Arty Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J14) that lets you use PC applications to communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller.
  
-The Zynq presets file (available in the [[reference:programmable-logic:arty-z7:start|Arty Z7 Resource Center]]) takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length.+The Zynq presets file (available in the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]]) takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length.
  
 Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD11) and the receive LED (LD10). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD11) and the receive LED (LD10). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.
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 ====== 7 microSD Slot ====== ====== 7 microSD Slot ======
  
-The Arty Z7 provides a microSD slot (J9) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including Card Detect. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 7.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.+The Arty Z7 provides a microSD slot (J9) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including Card Detect. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 7.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
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 //Table 7.1. microSD pinout// //Table 7.1. microSD pinout//
  
-The SD slot is a powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen on Figure 7.1. Mapping out the correct pins and configuring the interface is handled by the Arty Z7 Zynq presets file, available on the [[reference:programmable-logic:arty-z7:start|Arty Z7 Resource Center]].+The SD slot is a powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen on Figure 7.1. Mapping out the correct pins and configuring the interface is handled by the Arty Z7 Zynq presets file, available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]].
  
-{{ arty-z7-microsd.png?500 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-microsd.png?500 |}}
  
 //Figure 7.1. microSD slot signals// //Figure 7.1. microSD slot signals//
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 Both low speed and high speed cards are supported, the maximum clock frequency being 50 MHz. A Class 4 card or better is recommended.  Both low speed and high speed cards are supported, the maximum clock frequency being 50 MHz. A Class 4 card or better is recommended. 
  
-Refer to section 3.1 for information on how to boot from an SD card. For more information, consult the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+Refer to section 3.1 for information on how to boot from an SD card. For more information, consult the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 ====== 8 USB Host ====== ====== 8 USB Host ======
  
-The Arty Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported.  +The Arty Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Texas Instruments TUSB1210 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported.
  
-The Arty Z7 is technically an “embedded host”, because it does not provide the required 150 µF of capacitance on VBUS required to qualify as a general purpose host. It is possible to modify the Arty Z7 so that it complies with the general purpose USB host requirements by loading C41 with a 150 µF capacitor. Only those experienced at soldering small components on PCBs should attempt this rework. Many USB peripheral devices will work just fine without loading C41. Whether the Arty Z7 is configured as an embedded host or a general purpose host, it can provide 500 mA on the 5V VBUS line. Note that loading C41 may cause the Arty Z7 to reset when booting embedded Linux while powered from the USB port, regardless of if any USB device is connected to the host port. This is caused by the in-rush current that C41 causes when the USB host controller is enabled and the VBUS power switch (IC9) is turned on.+The Arty Z7 is technically a “general purpose host”, because it provides the required 150 µF of capacitance on VBUS. The Arty Z7 can provide 500 mA on the 5V VBUS line.
  
 Note that if your design uses the USB Host port (embedded or general purpose), then the Arty Z7 should be powered via a battery or wall adapter capable of providing more power (such as the one included in the Arty Z7 accessory kit).  Note that if your design uses the USB Host port (embedded or general purpose), then the Arty Z7 should be powered via a battery or wall adapter capable of providing more power (such as the one included in the Arty Z7 accessory kit). 
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 The Arty Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively.  The Arty Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. 
  
-{{ arty-z7-eth.png?500 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-eth.png?500 |}}
  
 //Figure 9.1. Ethernet PHY signals// //Figure 9.1. Ethernet PHY signals//
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 //Table 9.1. Ethernet status LEDs.// //Table 9.1. Ethernet status LEDs.//
  
-The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Arty Z7 Zynq Presets file, available on the [[reference:programmable-logic:arty-z7:start|Arty Z7 Resource Center]].+The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Arty Z7 Zynq Presets file, available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]].
  
 Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration. Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration.
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 The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source. The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source.
  
-On an Ethernet network each node needs a unique MAC address. To this end, the one-time-programmable (OTP) region of the Quad-SPI flash has been programmed at the factory with a 48-bit globally unique EUI-48/64™ compatible identifier. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address. Refer to the Flash memory datasheet that is associated for the chip loaded on the board (see the __[[reference:programmable-logic:arty-z7:reference-manual#quad_spi_flash|Quad SPI Flash]]__ section for more details) for information on how to access the OTP regions. When using Petalinux, this is automatically handled in the U-boot boot-loader, and the Linux system is automatically configured to use this unique MAC address.+On an Ethernet network each node needs a unique MAC address. To this end, the one-time-programmable (OTP) region of the Quad-SPI flash has been programmed at the factory with a 48-bit globally unique EUI-48/64™ compatible identifier. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address. Refer to the Flash memory datasheet that is associated for the chip loaded on the board (see the __[[programmable-logic:arty-z7:reference-manual#quad_spi_flash|Quad SPI Flash]]__ section for more details) for information on how to access the OTP regions. When using Petalinux, this is automatically handled in the U-boot boot-loader, and the Linux system is automatically configured to use this unique MAC address.
  
-For more information on using the Gigabit Ethernet MAC, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more information on using the Gigabit Ethernet MAC, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
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 The 19-pin HDMI connectors include three differential data channels, one differential clock channel five GND connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I2C bus, a Hot Plug Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. All non-power signals are wired to the Zynq PL with the exception of RES. The 19-pin HDMI connectors include three differential data channels, one differential clock channel five GND connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I2C bus, a Hot Plug Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. All non-power signals are wired to the Zynq PL with the exception of RES.
 +
 +Note that if you use the HDMI source port, in order to ensure the minimum level of the 5V signal is at least 4.8V as required by the HDMI specification, the Arty Z7 should be powered via a wall adapter (such as the one included in the Arty Z7 accessory kit); thus, the 5V level will be established by the IC24 on-board regulator. Otherwise, USB power can provide a voltage as low as 4.75V, which would be too low for the HDMI source port 5V signal.
  
 ^ Pin/Signal          ^ J11 (source)                                                      |^ <color #ed1c24>J10 (sink)</color>                                                                               || ^ Pin/Signal          ^ J11 (source)                                                      |^ <color #ed1c24>J10 (sink)</color>                                                                               ||
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 ====== 11 Clock Sources ====== ====== 11 Clock Sources ======
  
-The Arty Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Arty Z7 Zynq Presets file available on the [[reference:programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.+The Arty Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Arty Z7 Zynq Presets file available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.
  
 The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the PL. Additionally, the Arty Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor.  The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the PL. Additionally, the Arty Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor. 
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 Figure 11.1 outlines the clocking scheme used on the Arty Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low. Figure 11.1 outlines the clocking scheme used on the Arty Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low.
  
-{{ arty-z7-clocking.png?500 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-clocking.png?500 |}}
  
 //Figure 11.1. Arty Z7 clocking.// //Figure 11.1. Arty Z7 clocking.//
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 The Arty Z7 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4 individual LEDs as shown in Figure 12.1. The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button or slide switch was inadvertently defined as an output). The four push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position. The Arty Z7 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4 individual LEDs as shown in Figure 12.1. The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button or slide switch was inadvertently defined as an output). The four push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position.
  
-{{ arty-z7-gpio.png?500 |Figure 12.1. Arty Z7 GPIO.}}+{{ reference:programmable-logic:arty-z7:arty-z7-gpio.png?500 |Figure 12.1. Arty Z7 GPIO.}}
  
 //Figure 12.1. Arty Z7 GPIO.// //Figure 12.1. Arty Z7 GPIO.//
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 The on-board audio jack (J13) is driven by a Sallen-Key Butterworth Low-pass 4th Order Filter that provides mono audio output. The circuit of the low-pass filter is shown in Figure 14.1. The input of the filter (AUD_PWM) is connected to the Zynq PL pin R18. A digital input will typically be a pulse-width modulated (PWM) or pulse density modulated (PDM) open-drain signal produced by the FPGA. The signal needs to be driven low for logic ‘0’ and left in high-impedance for logic ‘1’. An on-board pull-up resistor to a clean analog 3.3V rail will establish the proper voltage for logic ‘1’. The low-pass filter on the input will act as a reconstruction filter to convert the pulse-width modulated digital signal into an analog voltage on the audio jack output. The on-board audio jack (J13) is driven by a Sallen-Key Butterworth Low-pass 4th Order Filter that provides mono audio output. The circuit of the low-pass filter is shown in Figure 14.1. The input of the filter (AUD_PWM) is connected to the Zynq PL pin R18. A digital input will typically be a pulse-width modulated (PWM) or pulse density modulated (PDM) open-drain signal produced by the FPGA. The signal needs to be driven low for logic ‘0’ and left in high-impedance for logic ‘1’. An on-board pull-up resistor to a clean analog 3.3V rail will establish the proper voltage for logic ‘1’. The low-pass filter on the input will act as a reconstruction filter to convert the pulse-width modulated digital signal into an analog voltage on the audio jack output.
  
-{{ arty-z7-audio-sch.png? |}}+{{ reference:programmable-logic:arty-z7:arty-z7-audio-sch.png? |}}
  
 //Figure 13.1. Audio Output Circuit.//  //Figure 13.1. Audio Output Circuit.// 
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 The frequency response of SK Butterworth Low-Pass Filter is shown in Figure 13.2. The AC analysis of the circuit is done using NI Multisim 12.0. The frequency response of SK Butterworth Low-Pass Filter is shown in Figure 13.2. The AC analysis of the circuit is done using NI Multisim 12.0.
  
-{{ arty-z7-audio-chart-nolabel.png?550 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-audio-chart-nolabel.png?550 |}}
  
 //Figure 13.2. Audio Output Frequency Response.// //Figure 13.2. Audio Output Frequency Response.//
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 A pulse-width modulated (PWM) signal is a chain of pulses at some fixed frequency, with each pulse potentially having a different width. This digital signal can be passed through a simple low-pass filter that integrates the digital waveform to produce an analog voltage proportional to the average pulse-width over some interval (the interval is determined by the 3dB cut-off frequency of the low-pass filter and the pulse frequency). For example, if the pulses are high for an average of 10% of the available pulse period, then an integrator will produce an analog value that is 10% of the Vdd voltage. Figure 13.1.1 shows a waveform represented as a PWM signal. A pulse-width modulated (PWM) signal is a chain of pulses at some fixed frequency, with each pulse potentially having a different width. This digital signal can be passed through a simple low-pass filter that integrates the digital waveform to produce an analog voltage proportional to the average pulse-width over some interval (the interval is determined by the 3dB cut-off frequency of the low-pass filter and the pulse frequency). For example, if the pulses are high for an average of 10% of the available pulse period, then an integrator will produce an analog value that is 10% of the Vdd voltage. Figure 13.1.1 shows a waveform represented as a PWM signal.
  
-{{ arty-z7-audio-pdm.png?600 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-audio-pdm.png?600 |}}
  
 //Figure 13.1.1. PWM Waveform.// //Figure 13.1.1. PWM Waveform.//
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 The PWM signal must be integrated to define an analog voltage. The low-pass filter 3dB frequency should be an order of magnitude lower than the PWM frequency, so that signal energy at the PWM frequency is filtered from the signal. For example, if an audio signal must contain up to 5 KHz of frequency information, then the PWM frequency should be at least 50 KHz (and preferably even higher). In general, in terms of analog signal fidelity, the higher the PWM frequency, the better. Figure 13.1.2 shows a representation of a PWM integrator producing an output voltage by integrating the pulse train. Note the steady-state filter output signal amplitude ratio to Vdd is the same as the pulse-width duty cycle (duty cycle is defined as pulse-high time divided by pulse-window time). The PWM signal must be integrated to define an analog voltage. The low-pass filter 3dB frequency should be an order of magnitude lower than the PWM frequency, so that signal energy at the PWM frequency is filtered from the signal. For example, if an audio signal must contain up to 5 KHz of frequency information, then the PWM frequency should be at least 50 KHz (and preferably even higher). In general, in terms of analog signal fidelity, the higher the PWM frequency, the better. Figure 13.1.2 shows a representation of a PWM integrator producing an output voltage by integrating the pulse train. Note the steady-state filter output signal amplitude ratio to Vdd is the same as the pulse-width duty cycle (duty cycle is defined as pulse-high time divided by pulse-window time).
  
-{{ arty-z7-audio-pwm.png?600 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-audio-pwm.png?600 |}}
  
 //Figure 13.1.2. PWM Output Voltage.//  //Figure 13.1.2. PWM Output Voltage.// 
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 ====== 14 Reset Sources ====== ====== 14 Reset Sources ======
  
-==== 14.1 Power-on Reset ====+==== 14.1 Power-on Reset Signals ====
  
 The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Arty Z7 drives this signal from the PGOOD signal of the TPS65400 power regulator in order to hold the system in reset until all power supplies are valid.  The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Arty Z7 drives this signal from the PGOOD signal of the TPS65400 power regulator in order to hold the system in reset until all power supplies are valid. 
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 **Warning:** //Since the Pmod pins are connected to Zynq PL I/O pins using a 3.3V logic standard, care should be taken not to drive these pins over 3.4V.// **Warning:** //Since the Pmod pins are connected to Zynq PL I/O pins using a 3.3V logic standard, care should be taken not to drive these pins over 3.4V.//
  
-{{ arty-z7-pmod.png?300 |}}+{{ reference:programmable-logic:arty-z7:arty-z7-pmod.png?300 |}}
 //Figure 15.1. Pmod Port Diagram// //Figure 15.1. Pmod Port Diagram//
  
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 **Warning:** //The Arty Z7 is not compatible with shields that output 5V digital or analog signals. Driving pins on the Arty Z7 shield connector above 3.4V may cause damage to the Zynq.// **Warning:** //The Arty Z7 is not compatible with shields that output 5V digital or analog signals. Driving pins on the Arty Z7 shield connector above 3.4V may cause damage to the Zynq.//
  
-{{ arty-z7-shield.png?direct&600 |Figure 16.1. Shield connector pin diagram.}}+{{ reference:programmable-logic:arty-z7:arty-z7-shield.png?direct&600 |Figure 16.1. Shield connector pin diagram.}}
  
 //Figure 16.1. Shield Pin Diagram.// //Figure 16.1. Shield Pin Diagram.//
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 //Table 16.1.1. Shield Digital Voltages.// //Table 16.1.1. Shield Digital Voltages.//
  
-For more information on the electrical characteristics of the pins connected to the Zynq PL, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf|Zynq-7000 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the Zynq PL, please see the [[https://docs.xilinx.com/v/u/en-US/ds187-XC7Z010-XC7Z020-Data-Sheet|Zynq-7000 datasheet]] from Xilinx.
  
 ==== 16.2 Shield Analog I/O ==== ==== 16.2 Shield Analog I/O ====
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 The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the Zynq. The Zynq expects that the inputs range from 0-1 V. On the pins labeled A0-A5 we use an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 16.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Arty Z7's GND) that is applied to any of these pins. If you wish to use the pins labeled A0-A5 as Digital inputs or outputs, they are also connected directly to the Zynq PL before the resistor divider circuit (also shown in Figure 16.2.1) on the Arty Z7-20. This additional connection is not made on the Arty Z7-10, which is why these signals can only be used as analog inputs on that variant. The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the Zynq. The Zynq expects that the inputs range from 0-1 V. On the pins labeled A0-A5 we use an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 16.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Arty Z7's GND) that is applied to any of these pins. If you wish to use the pins labeled A0-A5 as Digital inputs or outputs, they are also connected directly to the Zynq PL before the resistor divider circuit (also shown in Figure 16.2.1) on the Arty Z7-20. This additional connection is not made on the Arty Z7-10, which is why these signals can only be used as analog inputs on that variant.
  
-{{ arty-z7-shield-an.png?direct&600 |Figure 16.2.1. Single-Ended Analog Inputs}}+{{ reference:programmable-logic:arty-z7:arty-z7-shield-an.png?direct&600 |Figure 16.2.1. Single-Ended Analog Inputs}}
  
 //Figure 16.2.1. Single-Ended Analog Inputs.// //Figure 16.2.1. Single-Ended Analog Inputs.//
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 The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 16.2.2 for this pair of pins is loaded on the Arty Z7. The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 16.2.2 for this pair of pins is loaded on the Arty Z7.
  
-{{ arty-z7-shield-diff-an.png?direct&600 |Figure 16.2.2. Differential Analog Inputs}}+{{ reference:programmable-logic:arty-z7:arty-z7-shield-diff-an.png?direct&600 |Figure 16.2.2. Differential Analog Inputs}}
  
 //Figure 16.2.2. Differential Analog Inputs.// //Figure 16.2.2. Differential Analog Inputs.//
  
-The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
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 Although we strive to provide perfect products, we are not infallible. The Arty Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Arty Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^
-| Arty Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Arty (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Arty (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |+| Arty Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Arty (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Arty (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: [[https://support.xilinx.com/s/article/53039]]. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |
  
 {{tag>rm doc arty-z7}} {{tag>rm doc arty-z7}}