Arty Z7 XADC Demo

This project instantiates the XADC IP Core and measures an analog voltage, this simple XADC demo is a Verilog project made to demonstrate the ADC functionality of the Arty Z7. Only the programmable logic of the Arty Z7 is used.

• The LED associated with a specific channel brightens when the read voltage goes up.
• The two user switches enable two XADC channels to be read from.

This demo uses the chipKIT Analog connector, which has differential ports 1, 2, and 3 connected to the XADC pins 12, 0, and 8, respectively. This can be seen in the schematic below.

• Arty Z7 with a MicroUSB Programming Cable
• Vivado installation compatible with the latest release of this demo (2020.1)
  • See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
• Wires and a Circuit to Test

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users: All demos for the Arty Z7 are provided through the Arty-Z7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories (Redirect) page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

Set up the Arty Z7

Plug the Arty Z7 into the computer using the microUSB cable. The circuit and wires can be attached after the demo is already running.

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This page has been moved, the new location is Using a Digilent FPGA Github Demo's Releases (2020.1).

At this point, the demo is now running on your board. Refer to the Description and Functionality sections of this document for more information on what it does.

The demo reads analog data in from each enabled XADC channel (set the associated switch to the high position to enable that channel) and sets the brightness on the associated led linearly. Higher voltage = brighter led.

All materials related to the use of the Arty Z7 can be found on its Resource Center.

For a walkthrough of the process of creating a simple HDL project in Vivado, see Getting Started with Vivado for Hardware-Only Designs (Redirect). Information on important parts of the GUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.

{{tag>project arty-z7}}