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programmable-logic:arty-s7:reference-manual [2021/05/14 16:03] – ↷ Page moved from reference:programmable-logic:arty-s7:reference-manual to programmable-logic:arty-s7:reference-manual Arthur Brownprogrammable-logic:arty-s7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 ====== Software Support ====== ====== Software Support ======
  
-The Arty S7 is fully compatible with the high-performance Vivado ® Design Suite versions 2017.3 and newer. It is supported under the free WebPACK™ installation option - which does not require a license - so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs, the Logic Analyzer, and High-level Synthesis (HLS). The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. Design resources, example projects, and tutorials are available for download at the [[reference:programmable-logic:arty-s7:start|Arty S7 Resource Center]].+The Arty S7 is fully compatible with the high-performance Vivado ® Design Suite versions 2017.3 and newer. It is supported under the free WebPACK™ installation option - which does not require a license - so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs, the Logic Analyzer, and High-level Synthesis (HLS). The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. Design resources, example projects, and tutorials are available for download at the [[programmable-logic:arty-s7:start|Arty S7 Resource Center]].
  
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 The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Arty S7 resource center to speed up this process. It is included in the digilent-mig repository on the [[https://github.com/Digilent|Digilent Github]]. This download also includes a .prj file that can be imported into the wizard to automatically configure it with the options found in Table 3.1.  The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Arty S7 resource center to speed up this process. It is included in the digilent-mig repository on the [[https://github.com/Digilent|Digilent Github]]. This download also includes a .prj file that can be imported into the wizard to automatically configure it with the options found in Table 3.1. 
  
-For those using the MIG with a MicroBlaze project, it is not necessary to use the files found in the digilent-mig repository. Instead, the Arty S7 MIG settings and pinout will be automatically imported from the [[https://reference.digilentinc.com/reference/software/vivado/board-files|Digilent Vivado board files]].+For those using the MIG with a MicroBlaze project, it is not necessary to use the files found in the digilent-mig repository. Instead, the Arty S7 MIG settings and pinout will be automatically imported from the [[software/vivado/board-files|Digilent Vivado board files]].
  
 For more details on the Xilinx MIG, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586). For more details on the Xilinx MIG, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586).
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 ===== 4 Quad-SPI Flash ===== ===== 4 Quad-SPI Flash =====
  
-FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S), and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. A Spartan-7 50T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~13.92 MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into your bitstream, and then program the bitstream and large microblaze program into the Quad SPI Flash using Xilinx SDK. +FPGA configuration files can be written to the Quad-SPI Flash, and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. A Spartan-7 50T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~13.92 MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into your bitstream, and then program the bitstream and large microblaze program into the Quad SPI Flash using Xilinx SDK. 
  
-The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Spansion's datasheet for the flash device to learn how to implement a custom controller.+The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to the manufacturer's datasheet for the flash device to learn how to implement a custom controller.
  
 All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O, except for SCK. It can only be accessed by instantiating a special primitive called STARTUPE2. The Xilinx AXI Quad SPI IP core has a configuration option that will automatically instantiate the primitive for you, and this option should be enabled when using it with the Arty S7. For information on instantiating the primitive from HDL, refer to the "Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide" (UG953) from Xilinx.  All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O, except for SCK. It can only be accessed by instantiating a special primitive called STARTUPE2. The Xilinx AXI Quad SPI IP core has a configuration option that will automatically instantiate the primitive for you, and this option should be enabled when using it with the Arty S7. For information on instantiating the primitive from HDL, refer to the "Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide" (UG953) from Xilinx. 
 +
 +To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options.
 +^ Manufacturer ​      ^ P/N                       | PCB Revision ​                                         | Package Marking ​ |
 +| Spansion/​Infineon ​ | S25FL128SAG[M%%|%%N]FI00 ​ | <nowiki><=</nowiki> E w/o sticker OR >= E w/ sticker ​ | FL128SAIF00 ​     |
 +| Spansion/​Infineon ​ | S25FL127SABMFx00 ​         | >= E w/ sticker ​                                      | FL127SxF00 ​      |
 +//Table 4.1 Flash memory part loaded//
 +
 +The two part numbers are highly compatible and the "​s25fl128s-3.3v-qspi-x4-single"​ part configuration can be used in Vivado Hardware Manager for both. However, the S25FL127S is not functionally equivalent to the S25FL128S and might require changes to customer applications (embedded software) depending on the board support package in use (OS, drivers, and libraries). It might be possible to implement any changes that might be needed in such a way to keep compatibility with all load options.
 +A non-exhaustive list of the differences between the S25FL127S and the S25FL128S:
 +  * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to dynamically initialize the flash device instead of relying on a static configuration if the command is available.
 +  * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported
 +  * Memory organization:​ 255 64-KB and 16 4-KB bottom hybrid erase sectors vs. 254 64-KB and 32 4-KB bottom hybrid erase sectors
 +  * Maximum clock frequency: 108 MHz vs. 133MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Arty S7 applies.
 +
 +**Note:** //Refer to the manufacturer’s data sheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files|Spansion S25FL128S Datasheet]]
 +[[https://www.infineon.com/dgdl/Infineon-S25FL127S_128-Mb_(16_MB)_3.0_V_SPI_Flash_Memory-DataSheet-v11_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfa58c49f7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-datasheet|Spansion S25FL127S Datasheet]])] ​ and Xilinx user guides[([[https://docs.xilinx.com/v/u/en-US/ug470_7Series_Config|7-Series FPGAs Configuration User Guide from Xilinx]])] ​ for more information.//
  
 {{ :reference:programmable-logic:arty-s7:arty-s7-flash.png?550 |Figure 4.1. Arty S7 Quad SPI flash.}} {{ :reference:programmable-logic:arty-s7:arty-s7-flash.png?550 |Figure 4.1. Arty S7 Quad SPI flash.}}
 //Figure 4.1. Arty S7 SPI flash.// //Figure 4.1. Arty S7 SPI flash.//
 +
 +~~REFNOTES~~
  
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 ===== 9 Arduino/chipKIT Shield Connector ===== ===== 9 Arduino/chipKIT Shield Connector =====
  
-The Arty S7 can be connected to standard Arduino and chipKIT shields to add extended functionality. Special care was taken while designing the Arty S7 to make sure it is compatible with the majority of Arduino and chipKIT shields on the market. The shield connector has 45 pins connected to the FPGA for general purpose Digital I/O. Due to the flexibility of FPGAs, it is possible to use these pins for just about anything including digital read/write, SPI connections, UART connections, I2C connections, and PWM. Six of these pins (labeled AN0-AN5) can also be used as single-ended analog inputs with an input range of 0V-3.3V, and another four (labeled AN6-9) can be used as differential analog input pairs with an input range of 0V-1.0V. The Arty S7's shield connector is implemented on headers J1, J2, J3, J5, J6, and J8. For more information on how the shield connector pins are connected to the FPGA, refer to the Arty S7 schematic and master XDC file, available through the [[reference:programmable-logic:arty-s7:start|Arty S7 Resource Center]].+The Arty S7 can be connected to standard Arduino and chipKIT shields to add extended functionality. Special care was taken while designing the Arty S7 to make sure it is compatible with the majority of Arduino and chipKIT shields on the market. The shield connector has 45 pins connected to the FPGA for general purpose Digital I/O. Due to the flexibility of FPGAs, it is possible to use these pins for just about anything including digital read/write, SPI connections, UART connections, I2C connections, and PWM. Six of these pins (labeled AN0-AN5) can also be used as single-ended analog inputs with an input range of 0V-3.3V, and another four (labeled AN6-9) can be used as differential analog input pairs with an input range of 0V-1.0V. The Arty S7's shield connector is implemented on headers J1, J2, J3, J5, J6, and J8. For more information on how the shield connector pins are connected to the FPGA, refer to the Arty S7 schematic and master XDC file, available through the [[start|Arty S7 Resource Center]].
  
 **Warning:** //The Arty S7 is not compatible with shields that output 5V digital or analog signals. Driving pins on the Arty S7 shield connector above 3.4V may cause damage to the FPGA.// **Warning:** //The Arty S7 is not compatible with shields that output 5V digital or analog signals. Driving pins on the Arty S7 shield connector above 3.4V may cause damage to the FPGA.//
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 //Table 9.1.1. Shield Voltage Specifications// //Table 9.1.1. Shield Voltage Specifications//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf|Spartan-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds189-spartan-7-data-sheet|Spartan-7 datasheet]] from Xilinx.
  
 The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Arty S7, this can be done by placing two shorting blocks horizontally across the J4 header. The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Arty S7, this can be done by placing two shorting blocks horizontally across the J4 header.