Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
programmable-logic:arty-a7:reference-manual [2022/03/18 19:35] – Marthaprogrammable-logic:arty-a7:reference-manual [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 1: Line 1:
 ====== Arty A7 Reference Manual ====== ====== Arty A7 Reference Manual ======
-test 
  
 The Arty A7, formerly known as the Arty, is a ready-to-use development platform designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. It was designed specifically for use as a MicroBlaze Soft Processing System. When used in this context, the Arty A7 becomes the most flexible processing platform you could hope to add to your collection, capable of adapting to whatever your project requires. Unlike other Single Board Computers, the Arty A7 isn't bound to a single set of processing peripherals: One moment it's a communication powerhouse chock-full of UARTs, SPIs, IICs, and an Ethernet MAC, and the next it's a meticulous timekeeper with a dozen 32-bit timers. The Arty A7, formerly known as the Arty, is a ready-to-use development platform designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. It was designed specifically for use as a MicroBlaze Soft Processing System. When used in this context, the Arty A7 becomes the most flexible processing platform you could hope to add to your collection, capable of adapting to whatever your project requires. Unlike other Single Board Computers, the Arty A7 isn't bound to a single set of processing peripherals: One moment it's a communication powerhouse chock-full of UARTs, SPIs, IICs, and an Ethernet MAC, and the next it's a meticulous timekeeper with a dozen 32-bit timers.
Line 263: Line 262:
  
 **Note:** //Refer to the manufacturer’s data sheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files|Spansion S25FL128S Datasheet]] **Note:** //Refer to the manufacturer’s data sheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files|Spansion S25FL128S Datasheet]]
-[[https://www.infineon.com/dgdl/Infineon-S25FL127S_128-Mb_(16_MB)_3.0_V_SPI_Flash_Memory-DataSheet-v11_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfa58c49f7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-datasheet|Spansion S25FL127S Datasheet]])] ​ and Xilinx user guides[([[http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf|7-Series FPGAs Configuration User Guide from Xilinx]])] ​ for more information.//+[[https://www.infineon.com/dgdl/Infineon-S25FL127S_128-Mb_(16_MB)_3.0_V_SPI_Flash_Memory-DataSheet-v11_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfa58c49f7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-datasheet|Spansion S25FL127S Datasheet]])] ​ and Xilinx user guides[([[https://docs.xilinx.com/v/u/en-US/ug470_7Series_Config|7-Series FPGAs Configuration User Guide from Xilinx]])] ​ for more information.//
  
 {{ :arty:arty_spiflash.png?400 |Figure 5.2.1. Arty A7 SPI Flash.}} {{ :arty:arty_spiflash.png?400 |Figure 5.2.1. Arty A7 SPI Flash.}}
Line 430: Line 429:
 ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    | ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    |
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet|Artix-7 datasheet]] from Xilinx.
  
 ==== 11.2 Shield Analog I/O ==== ==== 11.2 Shield Analog I/O ====