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programmable-logic:arty-a7:reference-manual [2022/01/18 16:19] – [11.2 Shield Analog I/O] fix "used when using" Arthur Brownprogrammable-logic:arty-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 ==== 5.2 Quad-SPI Flash ==== ==== 5.2 Quad-SPI Flash ====
  
-FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number **S25FL128SAGMF100 for Rev. E** and Micron ​part number ​N25Q128A13ESF40 alias **mt25ql128 for Rev. C**), and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. Xilinx Answer Record 63605 explains how to do this.+FPGA configuration files can be written to the Quad-SPI Flash, and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. Xilinx Answer Record 63605 explains how to do this.
  
 The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, however, on the Arty A7 the SCK signal is routed to an additional general purpose pin that can be accessed after configuration (see Figure below). This allows access to this pin without having to instantiate the special FPGA primitive called STARTUPE2. The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, however, on the Arty A7 the SCK signal is routed to an additional general purpose pin that can be accessed after configuration (see Figure below). This allows access to this pin without having to instantiate the special FPGA primitive called STARTUPE2.
  
-Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Micron's datasheet for the flash device to learn how to implement a custom controller.+Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to the manufacturer's datasheet to learn how to implement a custom controller. 
 + 
 +To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options. 
 + 
 +^ Manufacturer ​      ^ P/N                       | PCB Revision ​                                            | Package Marking ​ | 
 +| Micron            ​ | N25Q128A13ESF40           | <nowiki><=</nowiki> C w/o sticker                                        ​ | N/A              | 
 +| Spansion/​Infineon ​ | S25FL128SAG[M%%|%%N]FI00 ​ | > C w/o sticker AND <nowiki><=</nowiki> E w/o sticker OR >= E w/ sticker ​ | FL128SAIF00 ​     | 
 +| Spansion/​Infineon ​ | S25FL127SABMFx00 ​         | >= E w/ sticker ​                                         | FL127SxF00 ​      | 
 +//Table 5.2.1 Flash memory part loaded// 
 + 
 +**Note:** //"mt25ql128" may be used as an alias for the Rev C's N25Q128A13ESF40 part in Vivado.// 
 + 
 +The two part numbers are highly compatible and the "​s25fl128s-3.3v-qspi-x4-single"​ part configuration can be used in Vivado Hardware Manager for both. However, the S25FL127S is not functionally equivalent to the S25FL128S and might require changes to customer applications (embedded software) depending on the board support package in use (OS, drivers, and libraries). It might be possible to implement any changes that might be needed in such a way to keep compatibility with all load options. 
 +A non-exhaustive list of the differences between the S25FL127S and the S25FL128S: 
 +  * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to  
 +dynamically initialize the flash device instead of relying on a static configuration if the command is available. 
 +  * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported 
 +  * Memory organization:​ 255 64-KB and 16 4-KB bottom hybrid erase sectors vs. 254 64-KB and 32 4-KB bottom hybrid erase sectors 
 +  * Maximum clock frequency: 108 MHz vs. 133MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Arty A7 applies. 
 + 
 +**Note:** //Refer to the manufacturer’s data sheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files|Spansion S25FL128S Datasheet]] 
 +[[https://www.infineon.com/dgdl/Infineon-S25FL127S_128-Mb_(16_MB)_3.0_V_SPI_Flash_Memory-DataSheet-v11_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfa58c49f7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-datasheet|Spansion S25FL127S Datasheet]])] ​ and Xilinx user guides[([[https://docs.xilinx.com/v/u/en-US/ug470_7Series_Config|7-Series FPGAs Configuration User Guide from Xilinx]])] ​ for more information.//
  
 {{ :arty:arty_spiflash.png?400 |Figure 5.2.1. Arty A7 SPI Flash.}} {{ :arty:arty_spiflash.png?400 |Figure 5.2.1. Arty A7 SPI Flash.}}
  
 //Figure 5.2.1 Arty A7 SPI Flash// //Figure 5.2.1 Arty A7 SPI Flash//
 +
 +~~REFNOTES~~
  
 ---- ----
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 ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    | ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    |
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet|Artix-7 datasheet]] from Xilinx.
  
 ==== 11.2 Shield Analog I/O ==== ==== 11.2 Shield Analog I/O ====