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| programmable-logic:arty-a7:reference-manual [2022/01/18 16:17] – Add Table 11.2.1 XADC Channel Connections Arthur Brown | programmable-logic:arty-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| ==== 5.2 Quad-SPI Flash ==== | ==== 5.2 Quad-SPI Flash ==== | ||
| - | FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number **S25FL128SAGMF100 for Rev. E** and Micron part number N25Q128A13ESF40 alias **mt25ql128 for Rev. C**), and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, | + | FPGA configuration files can be written to the Quad-SPI Flash, and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, |
| The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, | The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, | ||
| - | Xilinx' | + | Xilinx' |
| + | |||
| + | To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options. | ||
| + | |||
| + | ^ Manufacturer ^ P/N | PCB Revision | Package Marking | | ||
| + | | Micron | ||
| + | | Spansion/ | ||
| + | | Spansion/ | ||
| + | //Table 5.2.1 Flash memory part loaded// | ||
| + | |||
| + | **Note:** //" | ||
| + | |||
| + | The two part numbers are highly compatible and the " | ||
| + | A non-exhaustive list of the differences between the S25FL127S and the S25FL128S: | ||
| + | * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to | ||
| + | dynamically initialize the flash device instead of relying on a static configuration if the command is available. | ||
| + | * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported | ||
| + | * Memory organization: | ||
| + | * Maximum clock frequency: 108 MHz vs. 133MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Arty A7 applies. | ||
| + | |||
| + | **Note:** //Refer to the manufacturer’s data sheets[([[https:// | ||
| + | [[https:// | ||
| {{ : | {{ : | ||
| //Figure 5.2.1 Arty A7 SPI Flash// | //Figure 5.2.1 Arty A7 SPI Flash// | ||
| + | |||
| + | ~~REFNOTES~~ | ||
| ---- | ---- | ||
| Line 406: | Line 429: | ||
| ^ Unpowered | ^ Unpowered | ||
| - | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/ | + | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/ |
| ==== 11.2 Shield Analog I/O ==== | ==== 11.2 Shield Analog I/O ==== | ||
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| ---- | ---- | ||
| - | The shield analog I/O pins are mapped to XADC channels as described in Table 11.2.1. Take a look at the master XDC file found in the [[https:// | + | The shield analog I/O pins are mapped to XADC channels as described in Table 11.2.1. Take a look at the master XDC file found in the [[https:// |
| //Table 11.2.1 XADC Channel Connections// | //Table 11.2.1 XADC Channel Connections// | ||
| + | |<70% 40% 30% 30%>| | ||
| ^ Shield Connector Pin ^ XADC Channel | ^ Shield Connector Pin ^ XADC Channel | ||
| | V_P(+) / V_N(-) | | V_P(+) / V_N(-) | ||