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programmable-logic:arty-a7:reference-manual [2021/05/14 16:39] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:arty-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
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 ~~REFNOTES~~ ~~REFNOTES~~
  
-The Arty A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Arty Resource Center, accessible from reference.digilentinc.com.+The Arty A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the [[start|Arty A7 Resource Center]].
  
 {{ reference:programmable-logic:arty-a7:arty-a7-callout.png?800 |Arty A7 Callout Diagram.}} {{ reference:programmable-logic:arty-a7:arty-a7-callout.png?800 |Arty A7 Callout Diagram.}}
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 ==== 5.2 Quad-SPI Flash ==== ==== 5.2 Quad-SPI Flash ====
  
-FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number **S25FL128SAGMF100 for Rev. E** and Micron ​part number ​N25Q128A13ESF40 alias **mt25ql128 for Rev. C**), and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. Xilinx Answer Record 63605 explains how to do this.+FPGA configuration files can be written to the Quad-SPI Flash, and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, and program this file into SPI Flash using Xilinx SDK and Vivado. Xilinx Answer Record 63605 explains how to do this.
  
 The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, however, on the Arty A7 the SCK signal is routed to an additional general purpose pin that can be accessed after configuration (see Figure below). This allows access to this pin without having to instantiate the special FPGA primitive called STARTUPE2. The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, however, on the Arty A7 the SCK signal is routed to an additional general purpose pin that can be accessed after configuration (see Figure below). This allows access to this pin without having to instantiate the special FPGA primitive called STARTUPE2.
  
-Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Micron's datasheet for the flash device to learn how to implement a custom controller.+Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to the manufacturer's datasheet to learn how to implement a custom controller. 
 + 
 +To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options. 
 + 
 +^ Manufacturer ​      ^ P/N                       | PCB Revision ​                                            | Package Marking ​ | 
 +| Micron            ​ | N25Q128A13ESF40           | <nowiki><=</nowiki> C w/o sticker                                        ​ | N/A              | 
 +| Spansion/​Infineon ​ | S25FL128SAG[M%%|%%N]FI00 ​ | > C w/o sticker AND <nowiki><=</nowiki> E w/o sticker OR >= E w/ sticker ​ | FL128SAIF00 ​     | 
 +| Spansion/​Infineon ​ | S25FL127SABMFx00 ​         | >= E w/ sticker ​                                         | FL127SxF00 ​      | 
 +//Table 5.2.1 Flash memory part loaded// 
 + 
 +**Note:** //"mt25ql128" may be used as an alias for the Rev C's N25Q128A13ESF40 part in Vivado.// 
 + 
 +The two part numbers are highly compatible and the "​s25fl128s-3.3v-qspi-x4-single"​ part configuration can be used in Vivado Hardware Manager for both. However, the S25FL127S is not functionally equivalent to the S25FL128S and might require changes to customer applications (embedded software) depending on the board support package in use (OS, drivers, and libraries). It might be possible to implement any changes that might be needed in such a way to keep compatibility with all load options. 
 +A non-exhaustive list of the differences between the S25FL127S and the S25FL128S: 
 +  * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to  
 +dynamically initialize the flash device instead of relying on a static configuration if the command is available. 
 +  * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported 
 +  * Memory organization:​ 255 64-KB and 16 4-KB bottom hybrid erase sectors vs. 254 64-KB and 32 4-KB bottom hybrid erase sectors 
 +  * Maximum clock frequency: 108 MHz vs. 133MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Arty A7 applies. 
 + 
 +**Note:** //Refer to the manufacturer’s data sheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files|Spansion S25FL128S Datasheet]] 
 +[[https://www.infineon.com/dgdl/Infineon-S25FL127S_128-Mb_(16_MB)_3.0_V_SPI_Flash_Memory-DataSheet-v11_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfa58c49f7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-datasheet|Spansion S25FL127S Datasheet]])] ​ and Xilinx user guides[([[https://docs.xilinx.com/v/u/en-US/ug470_7Series_Config|7-Series FPGAs Configuration User Guide from Xilinx]])] ​ for more information.//
  
 {{ :arty:arty_spiflash.png?400 |Figure 5.2.1. Arty A7 SPI Flash.}} {{ :arty:arty_spiflash.png?400 |Figure 5.2.1. Arty A7 SPI Flash.}}
  
 //Figure 5.2.1 Arty A7 SPI Flash// //Figure 5.2.1 Arty A7 SPI Flash//
 +
 +~~REFNOTES~~
  
 ---- ----
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 The CK_RST signal (see the Arty A7 Schematic) is also connected to the FT2232HQ device via JP2. When JP2 is shorted, the FT2232HQ can trigger a Microblaze reset, mimicking the behavior of Arduino and chipKIT boards when sketches are loaded. Note the CK_RST signal is also connected to the red RESET button and the RST pin of J7 on the shield connector (these connections are not shown in the figure below). The CK_RST signal (see the Arty A7 Schematic) is also connected to the FT2232HQ device via JP2. When JP2 is shorted, the FT2232HQ can trigger a Microblaze reset, mimicking the behavior of Arduino and chipKIT boards when sketches are loaded. Note the CK_RST signal is also connected to the red RESET button and the RST pin of J7 on the shield connector (these connections are not shown in the figure below).
  
-The connections between the FT2232HQ and the Artix-7 are shown in Figure 6.+The connections between the FT2232HQ and the Artix-7 are shown in Figure 8.1.
  
 {{ :arty:arty_uart.png?350 |Figure 8.1. Arty A7 UART.}} {{ :arty:arty_uart.png?350 |Figure 8.1. Arty A7 UART.}}
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 ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    | ^ Unpowered               | -0.4 V                    | N/A                                    | N/A                                    | 0.55 V                    |
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix-7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet|Artix-7 datasheet]] from Xilinx.
  
 ==== 11.2 Shield Analog I/O ==== ==== 11.2 Shield Analog I/O ====
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 //Figure 11.2.1 Arty A7 Single-Ended Analog Inputs// //Figure 11.2.1 Arty A7 Single-Ended Analog Inputs//
 +
 +----
  
 The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 11.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O.  The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 11.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O. 
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 The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A demo that uses the XADC core is available on the Arty A7 Resource Center.   The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A demo that uses the XADC core is available on the Arty A7 Resource Center.  
 +
 +----
 +
 +The shield analog I/O pins are mapped to XADC channels as described in Table 11.2.1. Take a look at the master XDC file found in the [[https://github.com/Digilent/digilent-xdc|digilent-xdc]] repository on Github for more information, including location contraints to be used when constraining the dual-use analog/digital pins in either mode.
 +
 +//Table 11.2.1 XADC Channel Connections//
 +|<70% 40% 30% 30%>|
 +^ Shield Connector Pin  ^ XADC Channel             ^ Channel Type  ^
 +| V_P(+) / V_N(-)       | Dedicated Analog Inputs  | Differential  |
 +| A0                    | Channel 4                | Single-ended  |
 +| A1                    | Channel 5                | Single-ended  |
 +| A2                    | Channel 6                | Single-ended  |
 +| A3                    | Channel 7                | Single-ended  |
 +| A4                    | Channel 15               | Single-ended  |
 +| A5                    | Channel 0                | Single-ended  |
 +| A6(+) / A7(-)         | Channel 12               | Differential  |
 +| A8(+) / A9(-)         | Channel 13               | Differential  |
 +| A10(+) / A11(-)       | Channel 14               | Differential  |
  
 {{tag>rm doc arty-a7}} {{tag>rm doc arty-a7}}