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| programmable-logic:arty-a7:reference-manual [2021/05/14 16:03] – ↷ Page moved from reference:programmable-logic:arty-a7:reference-manual to programmable-logic:arty-a7:reference-manual Arthur Brown | programmable-logic:arty-a7:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| ~~REFNOTES~~ | ~~REFNOTES~~ | ||
| - | The Arty A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Arty Resource Center, accessible from reference.digilentinc.com. | + | The Arty A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the [[start|Arty A7 Resource Center]]. |
| - | {{ arty-a7-callout.png? | + | {{ reference: |
| ^ Callout | ^ Callout | ||
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| A power-good LED (LD11), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributorof [[http:// | A power-good LED (LD11), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributorof [[http:// | ||
| - | {{ arty-a7-rev-e-power.png |Figure 3.1 Arty A7 Power Circuit}} | + | {{ reference: |
| //Figure 3.1 Arty A7 Power Circuit// | //Figure 3.1 Arty A7 Power Circuit// | ||
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| The Arty A7 includes circuitry for monitoring the voltage of an external supply connected to Power Jack J13 or an external battery pack connected to Header J7. A voltage divider is used to scale the unregulated input voltage, VU, to be within the range (0-1V) that the on-chip 12-bit ADC is capable of measuring. The unregulated input voltage, VU, is divided by 16 and then fed into Auxiliary Channel 2 on the XADC of the Artix-7. Applications that wish to monitor the voltage of an external supply may configure Channel 2 of the XADC as a unipolar input and perform a conversion to receive a digital value corresponding to the input voltage. Figure 3.1.1 provides an overview of the circuitry that allows an external supply voltage to be monitored. | The Arty A7 includes circuitry for monitoring the voltage of an external supply connected to Power Jack J13 or an external battery pack connected to Header J7. A voltage divider is used to scale the unregulated input voltage, VU, to be within the range (0-1V) that the on-chip 12-bit ADC is capable of measuring. The unregulated input voltage, VU, is divided by 16 and then fed into Auxiliary Channel 2 on the XADC of the Artix-7. Applications that wish to monitor the voltage of an external supply may configure Channel 2 of the XADC as a unipolar input and perform a conversion to receive a digital value corresponding to the input voltage. Figure 3.1.1 provides an overview of the circuitry that allows an external supply voltage to be monitored. | ||
| - | {{ arty-a7-vu-mon.png |Figure 3.1.1 Monitoring External Supply Voltage}} | + | {{ reference: |
| //Figure 3.1.1 Monitoring External Supply Voltage// | //Figure 3.1.1 Monitoring External Supply Voltage// | ||
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| The Arty A7 includes circuitry for monitoring the current consumed by the FPGA core. The current is monitored by measuring the voltage across a 10 milliohm sense resistor that’s placed between the output of the DC-DC converter system (IC11, Channel 1) and the VCCINT network. A current sense amplifier (IC16, Texas Instruments INA199A1) connected across the sense resistor provides a gain of 50 and produces an output voltage of 500 millivolts per amp of current. Currents above 2 Amps will not damage the circuit or the FPGA, but will be reported as 2 Amps. The output of the current sense amplifier is fed into Auxiliary Channel 10 on the XADC of the Artix-7 FPGA. Applications that wish to monitor the current consumption of the FPGA Core and Block RAM may configure Channel 10 of the XADC as a unipolar input and perform a conversion to receive a digital value that corresponds to the amplified sense resistor voltage. This current sense circuit is capable of measuring current between 0 and 2 Amps. Figure 3.2.1 provides an overview of the circuitry that allows the FPGA Core Supply current to be monitored. | The Arty A7 includes circuitry for monitoring the current consumed by the FPGA core. The current is monitored by measuring the voltage across a 10 milliohm sense resistor that’s placed between the output of the DC-DC converter system (IC11, Channel 1) and the VCCINT network. A current sense amplifier (IC16, Texas Instruments INA199A1) connected across the sense resistor provides a gain of 50 and produces an output voltage of 500 millivolts per amp of current. Currents above 2 Amps will not damage the circuit or the FPGA, but will be reported as 2 Amps. The output of the current sense amplifier is fed into Auxiliary Channel 10 on the XADC of the Artix-7 FPGA. Applications that wish to monitor the current consumption of the FPGA Core and Block RAM may configure Channel 10 of the XADC as a unipolar input and perform a conversion to receive a digital value that corresponds to the amplified sense resistor voltage. This current sense circuit is capable of measuring current between 0 and 2 Amps. Figure 3.2.1 provides an overview of the circuitry that allows the FPGA Core Supply current to be monitored. | ||
| - | {{ arty-a7-vccint-mon.png |Figure 3.2.1 FPGA Core Supply Current Monitoring}} | + | {{ reference: |
| //Figure 3.2.1 FPGA Core Supply Current Monitoring// | //Figure 3.2.1 FPGA Core Supply Current Monitoring// | ||
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| The Arty A7 includes circuitry for monitoring the voltage of the 5 Volt supply as well as the current consumed from this supply. A voltage divider is used to scale the 5V input voltage to be within the range (0-1V) that the on-chip 12-bit ADC is capable of measuring. The 5V supply voltage is divided by 5.99 and then fed into Auxiliary Channel 1 on the XADC of the Artix-7 FPGA. A combination of a 5 milliohm current sense resistor and a current sense amplifier (IC15, Texas Instruments INA199A1) are used to produce an output voltage of 250 millivolts per amp of current.This current sense circuit is capable of measuring current between 0 and 2 Amps. Currents above 4 Amps will not damage the circuit or the FPGA, but will be reported as only 4 Amps. The output of the current sense amplifier is fed into Auxiliary Channel 9 on the XADC of the Artix-7 FPGA. Applications that wish to monitor the instantaneous power consumption of the Arty A7 may configure Channels 1 and 9 of the XADC as unipolar inputs and then perform a simultaneous conversion of the two channels to receive digital values that can be used to compute the instantaneous power consumption. Figure 3.3.1 provides an overview of the circuitry that allows the 5V supply power consumption to be monitored. | The Arty A7 includes circuitry for monitoring the voltage of the 5 Volt supply as well as the current consumed from this supply. A voltage divider is used to scale the 5V input voltage to be within the range (0-1V) that the on-chip 12-bit ADC is capable of measuring. The 5V supply voltage is divided by 5.99 and then fed into Auxiliary Channel 1 on the XADC of the Artix-7 FPGA. A combination of a 5 milliohm current sense resistor and a current sense amplifier (IC15, Texas Instruments INA199A1) are used to produce an output voltage of 250 millivolts per amp of current.This current sense circuit is capable of measuring current between 0 and 2 Amps. Currents above 4 Amps will not damage the circuit or the FPGA, but will be reported as only 4 Amps. The output of the current sense amplifier is fed into Auxiliary Channel 9 on the XADC of the Artix-7 FPGA. Applications that wish to monitor the instantaneous power consumption of the Arty A7 may configure Channels 1 and 9 of the XADC as unipolar inputs and then perform a simultaneous conversion of the two channels to receive digital values that can be used to compute the instantaneous power consumption. Figure 3.3.1 provides an overview of the circuitry that allows the 5V supply power consumption to be monitored. | ||
| - | {{ arty-a7-vu-mon.png |Figure 3.3.1 5V Supply Power Monitoring}} | + | {{ reference: |
| //Figure 3.3.1 5V Supply Power Monitoring// | //Figure 3.3.1 5V Supply Power Monitoring// | ||
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| ==== 5.2 Quad-SPI Flash ==== | ==== 5.2 Quad-SPI Flash ==== | ||
| - | FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number **S25FL128SAGMF100 for Rev. E** and Micron part number N25Q128A13ESF40 alias **mt25ql128 for Rev. C**), and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, | + | FPGA configuration files can be written to the Quad-SPI Flash, and setting the mode jumper will cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T configuration file requires 17,536,096 bits of memory, leaving about 87% of the flash device (or ~14MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory (typically 128 KB). These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into a single file (called an .mcs file) that also contains the bitstream and your custom Microblaze application, |
| The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, | The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration. On other boards, SCK is an exception because it remains a dedicated pin even after configuration, | ||
| - | Xilinx' | + | Xilinx' |
| + | |||
| + | To find out the exact memory part loaded, check the PCB revision and any stickers placed on the PCB with the flash part number printed on it. The table below lists the possible load options. | ||
| + | |||
| + | ^ Manufacturer ^ P/N | PCB Revision | Package Marking | | ||
| + | | Micron | ||
| + | | Spansion/ | ||
| + | | Spansion/ | ||
| + | //Table 5.2.1 Flash memory part loaded// | ||
| + | |||
| + | **Note:** //" | ||
| + | |||
| + | The two part numbers are highly compatible and the " | ||
| + | A non-exhaustive list of the differences between the S25FL127S and the S25FL128S: | ||
| + | * Read SFDP command (5Ah) is supported now. The Linux kernel driver is known to probe this command and use the SFDP feature to | ||
| + | dynamically initialize the flash device instead of relying on a static configuration if the command is available. | ||
| + | * DDR Fast Read (0Dh, 0Eh), DDR Dual I/O Read (BDh, BEh), and Read DDR Quad I/O (EDh, EEh) not supported | ||
| + | * Memory organization: | ||
| + | * Maximum clock frequency: 108 MHz vs. 133MHz. Practically however, the system board limit is usually lower. The 50 MHz read/write maximum frequency of the Arty A7 applies. | ||
| + | |||
| + | **Note:** //Refer to the manufacturer’s data sheets[([[https:// | ||
| + | [[https:// | ||
| {{ : | {{ : | ||
| //Figure 5.2.1 Arty A7 SPI Flash// | //Figure 5.2.1 Arty A7 SPI Flash// | ||
| + | |||
| + | ~~REFNOTES~~ | ||
| ---- | ---- | ||
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| The CK_RST signal (see the Arty A7 Schematic) is also connected to the FT2232HQ device via JP2. When JP2 is shorted, the FT2232HQ can trigger a Microblaze reset, mimicking the behavior of Arduino and chipKIT boards when sketches are loaded. Note the CK_RST signal is also connected to the red RESET button and the RST pin of J7 on the shield connector (these connections are not shown in the figure below). | The CK_RST signal (see the Arty A7 Schematic) is also connected to the FT2232HQ device via JP2. When JP2 is shorted, the FT2232HQ can trigger a Microblaze reset, mimicking the behavior of Arduino and chipKIT boards when sketches are loaded. Note the CK_RST signal is also connected to the red RESET button and the RST pin of J7 on the shield connector (these connections are not shown in the figure below). | ||
| - | The connections between the FT2232HQ and the Artix-7 are shown in Figure | + | The connections between the FT2232HQ and the Artix-7 are shown in Figure |
| {{ : | {{ : | ||
| Line 406: | Line 429: | ||
| ^ Unpowered | ^ Unpowered | ||
| - | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/ | + | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/ |
| ==== 11.2 Shield Analog I/O ==== | ==== 11.2 Shield Analog I/O ==== | ||
| Line 415: | Line 438: | ||
| //Figure 11.2.1 Arty A7 Single-Ended Analog Inputs// | //Figure 11.2.1 Arty A7 Single-Ended Analog Inputs// | ||
| + | |||
| + | ---- | ||
| The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 11.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O. | The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 11.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O. | ||
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| The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A demo that uses the XADC core is available on the Arty A7 Resource Center. | The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A demo that uses the XADC core is available on the Arty A7 Resource Center. | ||
| + | |||
| + | ---- | ||
| + | |||
| + | The shield analog I/O pins are mapped to XADC channels as described in Table 11.2.1. Take a look at the master XDC file found in the [[https:// | ||
| + | |||
| + | //Table 11.2.1 XADC Channel Connections// | ||
| + | |<70% 40% 30% 30%>| | ||
| + | ^ Shield Connector Pin ^ XADC Channel | ||
| + | | V_P(+) / V_N(-) | ||
| + | | A0 | Channel 4 | Single-ended | ||
| + | | A1 | Channel 5 | Single-ended | ||
| + | | A2 | Channel 6 | Single-ended | ||
| + | | A3 | Channel 7 | Single-ended | ||
| + | | A4 | Channel 15 | Single-ended | ||
| + | | A5 | Channel 0 | Single-ended | ||
| + | | A6(+) / A7(-) | Channel 12 | Differential | ||
| + | | A8(+) / A9(-) | Channel 13 | Differential | ||
| + | | A10(+) / A11(-) | ||
| {{tag>rm doc arty-a7}} | {{tag>rm doc arty-a7}} | ||