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playground:ase-release-checklist [2018/01/12 21:23] – Arthur Brownplayground:ase-release-checklist [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ===== FPGA ===== ===== FPGA =====
  
-  * **Resource Center**: [[https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start|Example]].+  * **Resource Center**: [[/reference/programmable-logic/arty-z7/start|Example]].
     * **Schematics**     * **Schematics**
 +    * 3D CAD File
   * Hackster.io: how will we do this?   * Hackster.io: how will we do this?
-  * **Reference Manual**: [[https://reference.digilentinc.com/reference/programmable-logic/arty-z7/reference-manual|Example]]+  * **Reference Manual**: [[/reference/programmable-logic/arty-z7/reference-manual|Example]]
     * **Product Introduction**: to be shared with the Resource Center.     * **Product Introduction**: to be shared with the Resource Center.
     * **Feature List**: to be (partially) shared with the Resource Center.     * **Feature List**: to be (partially) shared with the Resource Center.
     * Documentation of the subsections required in an FPGA reference manual should be explained in another document.     * Documentation of the subsections required in an FPGA reference manual should be explained in another document.
-  * **Out-of-Box Demo**: The demo that is programmed onto the board at time of manufacturing. To be distributed via the Resource Center. This has not always been provided for our boards, but distribution of sources for this should be a high priority based on customer feedback.+  * **Out-of-Box Demo**: The demo that is programmed onto the board at time of manufacturing. To be distributed via the Resource Center. This has not always been provided for our boards, but distribution of sources for this should be a high priority based on customer feedback. This demo should demonstrate the use of the majority of major features on the board, including Ethernet connectivity, GPIO, video, etc.
   * **At least one Microblaze/Zynq and one pure-HDL demo**   * **At least one Microblaze/Zynq and one pure-HDL demo**
-  * Other demos: Including but not limited to the following: +  * Other demos: Listed according to priority. Including but not limited to the following: 
-    * Basic I/O+    * Basic I/O: Typically will be the pure-HDL demo 
 +    * Video (HDMI-In / HDMI-Out, etc.): First consideration for a Microblaze/Zynq demo, if hardware supports video.
     * XADC     * XADC
-    * Video (HDMI-In / HDMI-Out, etc.) 
     * Audio     * Audio
   * **Tutorial Content**: Make sure that all tutorials linked from the Resource Center work as intended without creating more edge cases.   * **Tutorial Content**: Make sure that all tutorials linked from the Resource Center work as intended without creating more edge cases.
     * **XDC File**: Distributed via the [[https://github.com/Digilent/digilent-xdc|digilent-xdc repository]] linked on the Resource Center for the      * **XDC File**: Distributed via the [[https://github.com/Digilent/digilent-xdc|digilent-xdc repository]] linked on the Resource Center for the 
-    * board through the use of the [[https://reference.digilentinc.com/learn/programmable-logic/doc/github/digilent-xdc?do=edit|shared redirect wiki page]].+    * board through the use of the [[/learn/programmable-logic/doc/github/digilent-xdc?do=edit|shared redirect wiki page]].
   * **Board Files**: Distributed via the [[https://github.com/Digilent/vivado-boards|vivado-boards repository]] linked through the Vivado installation tutorial flow. Separate board files must be created for different variants of a board. Board files should support the following IP:   * **Board Files**: Distributed via the [[https://github.com/Digilent/vivado-boards|vivado-boards repository]] linked through the Vivado installation tutorial flow. Separate board files must be created for different variants of a board. Board files should support the following IP:
     * **Xilinx Memory Interface Generator**: Microblaze-Only, to make configuration of the DDR3 interface easy. (mig.prj)     * **Xilinx Memory Interface Generator**: Microblaze-Only, to make configuration of the DDR3 interface easy. (mig.prj)
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   * SDSoC Platform   * SDSoC Platform
   * Vivado HLS Example Project   * Vivado HLS Example Project
 +
 ---- ----
 ===== Microcontroller ===== ===== Microcontroller =====
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   * **Resource Center**   * **Resource Center**
     * **Schematics**     * **Schematics**
 +    * 3D CAD File
   * **Demonstration Project / Library / Bootloader**: [[https://github.com/Digilent/Basys-MX3-library|Example]]   * **Demonstration Project / Library / Bootloader**: [[https://github.com/Digilent/Basys-MX3-library|Example]]
   * **Digilent Core Support**   * **Digilent Core Support**
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   * **Resource Center**   * **Resource Center**
     * **Schematics**     * **Schematics**
 +    * 3D CAD File
     * **Demonstration Projects**     * **Demonstration Projects**
       * **Pmod IP Core**       * **Pmod IP Core**
 +      * **Microcontroller Library/Demo**
       * HDL module / FPGA demo: this is not currently standard, but occasionally comes up on the forums       * HDL module / FPGA demo: this is not currently standard, but occasionally comes up on the forums
   * **Reference Manual**   * **Reference Manual**
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     * **Additional Information**: links to datasheets of important chips, schematics, demo projects, etc.     * **Additional Information**: links to datasheets of important chips, schematics, demo projects, etc.
   * **Hackster Product Entry**   * **Hackster Product Entry**
-  * **Microcontroller Library/Demo**