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playground:ase-release-checklist [2018/01/11 00:49] – [FPGA] Arthur Brownplayground:ase-release-checklist [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 This document describes the ASE materials that need to be created before a product is released. This is organized first by //product//, then by //category// of material, then by relative //priority// of the thing to be created. Priority is only split between //required// (**bold**) and suggested (not bold). This document describes the ASE materials that need to be created before a product is released. This is organized first by //product//, then by //category// of material, then by relative //priority// of the thing to be created. Priority is only split between //required// (**bold**) and suggested (not bold).
  
-Requirements for ASE to begin work on release materials primarily consist of a schematic and a specification sheet. I am not sure how well defined the list of things that will be on the specifications sheet is for non-FPGA products, but these two documents are the minimum at least for FPGAs. With Pmods, we can //usually// work from only a schematic, but more information may or may not be required, depending on the amount of custom work done on the hardware surrounding the Primary IC.+Requirements for ASE to begin work on release materials primarily consist of a schematic and a specification sheet. I am not sure how well defined the list of things that will be on the specifications sheet is for non-FPGA products, but these two documents are the minimum at least for FPGAs. With Pmods, we can //usually// work from only a schematic, but more information may or may not be required, depending on the amount of custom work done on the hardware surrounding the Primary IC. Product Photos are required for ASE to complete work.
  
 ===== FPGA ===== ===== FPGA =====
  
-=== Product Pages === +  * **Resource Center**: [[/reference/programmable-logic/arty-z7/start|Example]].
-  * **Resource Center**: [[https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start|Example]]. Resources to be included on this page are as follows:+
     * **Schematics**     * **Schematics**
-    * **Links to appropriate tutorials and Xilinx documentation** +    * 3D CAD File
-    * FIXME: complete list+
   * Hackster.io: how will we do this?   * Hackster.io: how will we do this?
- +  * **Reference Manual**: [[/reference/programmable-logic/arty-z7/reference-manual|Example]]
-=== Documentation === +
-  * **Reference Manual**: [[https://reference.digilentinc.com/reference/programmable-logic/arty-z7/reference-manual|Example]]+
     * **Product Introduction**: to be shared with the Resource Center.     * **Product Introduction**: to be shared with the Resource Center.
     * **Feature List**: to be (partially) shared with the Resource Center.     * **Feature List**: to be (partially) shared with the Resource Center.
     * Documentation of the subsections required in an FPGA reference manual should be explained in another document.     * Documentation of the subsections required in an FPGA reference manual should be explained in another document.
- +  * **Out-of-Box Demo**: The demo that is programmed onto the board at time of manufacturing. To be distributed via the Resource Center. This has not always been provided for our boards, but distribution of sources for this should be a high priority based on customer feedback. This demo should demonstrate the use of the majority of major features on the board, including Ethernet connectivity, GPIO, video, etc. 
-=== Demos === +  * **At least one Microblaze/Zynq and one pure-HDL demo** 
-To be distributed on the Resource Center for the board. +  * Other demos: Listed according to priority. Including but not limited to the following: 
- +    * Basic I/O: Typically will be the pure-HDL demo 
-  * **Out-of-Box Demo**: The demo that is programmed onto the board at time of manufacturing. To be distributed via the Resource Center. This has not always been provided for our boards, but distribution of sources for this should be a high priority based on customer feedback. (No up-to-date example) +    * Video (HDMI-In / HDMI-Out, etc.): First consideration for a Microblaze/Zynq demo, if hardware supports video.
-  * At least one Microblaze/Zynq and one pure-HDL demo +
-  * Other demos: Including but not limited to the following: +
-    * Basic I/O+
     * XADC     * XADC
-    * Video (HDMI-In / HDMI-Out, etc.) 
     * Audio     * Audio
   * **Tutorial Content**: Make sure that all tutorials linked from the Resource Center work as intended without creating more edge cases.   * **Tutorial Content**: Make sure that all tutorials linked from the Resource Center work as intended without creating more edge cases.
- +    * **XDC File**: Distributed via the [[https://github.com/Digilent/digilent-xdc|digilent-xdc repository]] linked on the Resource Center for the  
-=== Additional Materials === +    * board through the use of the [[/learn/programmable-logic/doc/github/digilent-xdc?do=edit|shared redirect wiki page]].
- +
-  * **XDC File**: Distributed via the [[https://github.com/Digilent/digilent-xdc|digilent-xdc repository]] linked on the Resource Center for the board through the use of the [[https://reference.digilentinc.com/learn/programmable-logic/doc/github/digilent-xdc?do=edit|shared redirect wiki page]].+
   * **Board Files**: Distributed via the [[https://github.com/Digilent/vivado-boards|vivado-boards repository]] linked through the Vivado installation tutorial flow. Separate board files must be created for different variants of a board. Board files should support the following IP:   * **Board Files**: Distributed via the [[https://github.com/Digilent/vivado-boards|vivado-boards repository]] linked through the Vivado installation tutorial flow. Separate board files must be created for different variants of a board. Board files should support the following IP:
     * **Xilinx Memory Interface Generator**: Microblaze-Only, to make configuration of the DDR3 interface easy. (mig.prj)     * **Xilinx Memory Interface Generator**: Microblaze-Only, to make configuration of the DDR3 interface easy. (mig.prj)
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       * Other interfaces may be added to this list as good solutions are found.       * Other interfaces may be added to this list as good solutions are found.
   * **Hackster Product Entry**   * **Hackster Product Entry**
 +  * Petalinux Base System and BSP
 +  * SDSoC Platform
 +  * Vivado HLS Example Project
  
 ---- ----
 ===== Microcontroller ===== ===== Microcontroller =====
  
-NOTE: As I am less familiar with this product category, more exploration of existing resources will be required. +  * **Reference Manual**: entries below are considered special when compared to the other sections. 
- +    * **Product Introduction**: sometimes created by Marketing 
-  * **Reference Manual**+    * **Feature List**: sometimes created by Marketing 
 +    * **Callout Table**: requires top-down product photo to work from
   * **Resource Center**   * **Resource Center**
-  * **Demonstration Projects** +    * **Schematics** 
-  * **Arduino IDE Support Files** - How do we currently do this?+    * 3D CAD File 
 +  * **Demonstration Project / Library / Bootloader**: [[https://github.com/Digilent/Basys-MX3-library|Example]] 
 +  * **Digilent Core Support**
   * **Hackster Product Entry**   * **Hackster Product Entry**
-  * Schematics / Other Documentation? 
  
 ---- ----
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   * **Resource Center**   * **Resource Center**
     * **Schematics**     * **Schematics**
 +    * 3D CAD File
     * **Demonstration Projects**     * **Demonstration Projects**
       * **Pmod IP Core**       * **Pmod IP Core**
-      * HDL module / FPGA demo - this is not currently standard, but occasionally comes up on the forums+      * **Microcontroller Library/Demo** 
 +      * HDL module / FPGA demo: this is not currently standard, but occasionally comes up on the forums
   * **Reference Manual**   * **Reference Manual**
     * **Product Introduction**     * **Product Introduction**
     * **Feature List**     * **Feature List**
-    * **Specifications**: consists primarily of pinout and physical dimensions +    * **Quickstart Guide**: this should be a step-by-step guide that walks through the configuration of the Pmod and the transmission or reception of the first packet of data to/from the Pmod, at the Protocol level (describe the set of I2C transactions, not the full bit-banged timing).
-    * **Functional Description** +
-      * **Quickstart Guide**: this should be a step-by-step guide that walks through the configuration of the Pmod and the transmission or reception of the first packet of data to/from the Pmod, at the Protocol level (describe the set of I2C transactions, not the full bit-banged timing).+
     * **Additional Information**: links to datasheets of important chips, schematics, demo projects, etc.     * **Additional Information**: links to datasheets of important chips, schematics, demo projects, etc.
   * **Hackster Product Entry**   * **Hackster Product Entry**
-  * **Microcontroller Library/Demo**