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nexys4_ddr:getting_started_with_vivado_ip_integrator [2014/12/22 21:28] – Varun Kondagunturinexys4_ddr:getting_started_with_vivado_ip_integrator [2014/12/22 23:32] (current) – removed sbobrowicz
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-When you first run Vivado this will be the main start window where you can create a new project or open a recent one. 
  
-1. Click on Create New Project. Choose the Project Name and Location such that there are no blank spaces. It is important to practice this rule when working with all Xilinx Tools. Project names, File names and Location Paths must not contain empty spaces. Using underscore in place of an empty space is recommended. 
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-It is also good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects. 
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-Name your Project and select the Project location and click next.  
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-{{:vivado:mig_1.jpg?1000|}} 
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-2. Choose Project Type as RTL Project. Leave the - do not specify sources box unchecked and click next. 
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-{{:vivado:mig_1-1.jpg?1000|}} 
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-3. If you have followed the instructions for saving Board Support Files in the Xilinx Installation directory ...  
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-Click on Boards and choose from the filter options below, make the selections for Vendor, Display Name and Board Revision. Nexys4 DDR should be displayed in the selection list. Make sure this is the Board you have with you and click next. 
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-{{:vivado:mig_2.jpg?1000|}} 
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-4. A summary of the new project design sources and target device is displayed. Click Finish. 
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-{{:vivado:mig_3.jpg?1000|}} 
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-5. This is the main project window where you can add design or create design sources, perform simulation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. 
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-{{:vivado:mig_4.jpg|}} 
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-6. On the left you should see the Flow Navigator. Select Create Block Design under the IP Integrator. Give a name to your design without any blank spaces. 
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-{{:vivado:mig_5.jpg|}} 
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-7. An empty design space is created where you can add IP blocks. You can click on the "Add IP" message prompt on the top or click on the yellow rectangular box with a green "+" on it. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for "Microblaze" and double click on it to add the IP block to your empty design.  
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-{{:vivado:mig_6.jpg|}} 
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-8. This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the "Run Block Automation" message prompt or by double clicking on the block itself. 
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-{{:vivado:mig_7.jpg|}} 
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-9. Block automation window will open up. 
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-{{:vivado:mig_8.jpg|}} 
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-10. Select block options as shown below and click ok. 
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-{{:vivado:mig_9.jpg|}} 
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-10. Running the block automation will auto-generate a set of additional IP blocks as part of your design based on the options selected in the previous step. Do not click on Run Connection Automation yet. 
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-{{:vivado:mig_11.jpg|}} 
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-11. Double click on the Clock Wizard (clk_wiz_1) IP block. 
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-{{:vivado:mig_12.jpg|}} 
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-12. Choose sys clock for CLK_IN1. 
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-{{:vivado:mig_13.jpg|}} 
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-13. Select the output Clocks tab. 
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-{{:vivado:mig_14.jpg|}} 
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-14. Select clk_out2 output frequency as 200.000 (Mhz) and set Reset type as Active Low. Now the reset pin should be displayed as "resetn" for active low. 
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-{{:vivado:mig_15.jpg|}} 
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-15. Moving to the Port Renaming view will give you a summary of the inputs and outputs to the Clock Wizard block.Click ok to finish block automation of Clock Wizard. 
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-{{:vivado:mig_16.jpg|}} 
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-16. Do not run connection automation yet. Select the Add IP as shown and search for UART. 
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-{{:vivado:mig_17.jpg|}} 
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-17. Select the "AXI Uartlite" IP block. 
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-{{:vivado:mig_18.jpg|}} 
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-18. This will add a UART block to the existing design. We need a UART controller to display the "Hello World" message in the terminal. 
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-{{:vivado:mig_19.jpg|}} 
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-19. Now select the "Run Connection Automation" from the Designer Assistance Bar message prompt. This will open up the Run Connection Automation window. Select the "ext_reset_in" as shown. A description of the interface will be shown along with the signal options. Select "reset" as the board part interface. 
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-{{:vivado:mig_20.jpg|}} 
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-20. Select all available connections. Completing this step will connect all the IP blocks that have been added and customized up to this point.  
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-{{:vivado:mig_21.jpg|}} 
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-21. Manually connect main "reset" pin to "resetn" input of clk_wiz_1 block. Place your cursor pointer on the "resetn" input and you should see the cursor change into a pen. Drag and drop anywhere on the reset line. 
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-{{:vivado:mig_22.jpg|}} 
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-22. Do not select Run Connection Automation at this point.  
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-{{:vivado:mig_23.jpg|}} 
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-23. Memory Interface Generator will be the final IP block to add in the design.  
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-{{:vivado:mig_24.jpg|}} 
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-24. After adding the MIG IP block, double click on the block to Run Block Automation.  
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-{{:vivado:mig_25.jpg|}} 
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-25. Board part interface will be displayed as DDR2_SDRAM. 
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-{{:vivado:mig_26.jpg|}} 
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-26. When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys4 DDR. 
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-{{:vivado:mig_27.jpg|}} 
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-27. Now click on Run Connection Automation. 
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-{{:vivado:mig_28.jpg|}} 
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-28. Select only the mig_7series_0 in the connection automation list. Do not select Microblaze in this step.  
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-{{:vivado:mig_29.jpg|}} 
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-29. New connections will be displayed.  
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-{{:vivado:mig_30.jpg|}} 
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-30. Manually connect clk_out2 output port signal on the clk_wiz_1 to the sys_clk_i input port on the mig_7series_ block. clk_out2 is the 200 Mhz clock signal we have added during the Clock Wizard block automation step.  
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-{{:vivado:mig_31.jpg|}} 
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-31 Select the button shown below. This is the "Regenerate Layout" option that will rearrange the IP blocks in the design. 
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-{{:vivado:mig_32.jpg|}} 
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-32. The right most top block is the MIG. Right click on the DDR2 port and select "Make External". 
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-{{:vivado:mig_33.jpg|}} 
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-33. This will create a new output port connection labeled as DDR2. 
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-{{:vivado:mig_34.jpg|}} 
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-34. Regenerate the layout one more time.  
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-{{:vivado:mig_35.jpg|}} 
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-35. Select Validate Design. This will check for any design and connection errors.  
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-{{:vivado:mig_36.jpg|}} 
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-36. After the design validation step has been successful we will now proceed with creating a HDL System Wrapper.  
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-{{:vivado:mig_37.jpg|}} 
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-37. As highlighted in this step, right click on "design_1" and select "Create System Wrapper". Let Vivado manage the wrapper. 
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-{{:vivado:mig_38.jpg|}} 
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-38. A system wrapper file will be generated and a message will be displayed in the tcl console informing you regarding this. 
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-{{:vivado:mig_39.jpg|}} 
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-39. In the FLow Navigator panel on the left, under Program and Debug -> there is the Generate Bitstream option. Select this to create Bitstream. If you haven't already saved your design, you will get a prompt to save the block design.  
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-{{:vivado:mig_40.jpg|}} 
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-The bit file generation will begin. The tool will run Synthesis and Implementation. After both synthesis and implementation have been successfully completed, the actual bit file will be created.  
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-{{:vivado:mig_41.jpg|}} 
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-40. After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just hit Cancel.  
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-{{:vivado:mig_42.jpg|}} 
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-41. On the top left from the tool bar, click on File and select Export Hardware.This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. Make sure the generated bitstream is included by checking the box. 
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-{{:vivado:mig_43.jpg|}} 
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-42. A new file directory will be created under Hello_World.SDK similar to the Vivado hardware design project name.  
-Two other files, .sysdef and .hdf are also created. This essentially creates a new SDK workspace. If you browse to the location on the drive where the Vivado project has been created, you will see new folders have been created under SDK. See TCL Console message in the screen capture below. Now that the design has been exported to Software Development Tool (SDK), the next step will be to launch the SDK tool. 
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-{{:vivado:mig_44.jpg|}} 
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-43. Go to File and select Launch SDK and click ok. The SDK file created local to the Vivado design project location will be launched.  
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-{{:vivado:mig_45.jpg|}} 
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-44. A new window for SDK will open. The HW design specifications and included IP blocks are displayed in the system.hdf file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design.  
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-Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits. After which you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.  
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-Since we do not have any HW design edits at this point, we will proceed with creating a software application to display Hello World. 
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-{{:vivado:mig_46.jpg|}} 
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-45. On the left of the main SDK window, you will find the project explorer panel.  
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-Notice the name "design_1_wrapper_hw_platform_0".  design_1 : is the name of your block design. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.  
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-If at this point, you close SDK, make edits to your existing hardware design, and export your design to SDK. After launching the SDK tool, you will find a new hardware platform called, "design_1_wrapper_hw_platform_1" in addition to the old HW design i.e. "design_1_wrapper_hw_platform_0". 
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-{{:vivado:mig_47.jpg|}} 
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-Go to File on the main tool bar and select New Application Project. A new project window will pop up.  
-Give your SDK project a name that has no blank spaces as shown below. Make sure the Target Hardware is the desired hardware design. In our case, it will be "design_1_wrapper_hw_platform_0".  
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-If for example, you also have another hardware design in the Project Explorer window, then you will see that design name in the Target Hardware drop down selection list.  
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-Also select, Create New under Board Support Package. The tool will automatically populate the Board Support Package name to match with the give project name.  
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-Click Next. 
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-{{:vivado:mig_48.jpg|}} 
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-Select Hello World under Available Templates on the left and click Finish.  
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-{{:vivado:mig_49.jpg|}} 
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-After completing the previous step, you will see two new folders in the Project Explorer panel.  
-One is the "display_hello_world" project folder. This contains all the binaries, .C and .H (Header) files.  
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-Also make note of another important file shown here which is the "lscript.ld". This is a Xilinx auto generated linker script. Double click on this file to open. 
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-{{:vivado:mig_50.jpg|}} 
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-In the linker script, take a look at the "Section to Memory Region Mapping" box. The target memory region MUST say, "mig_7series_0". Scroll down to check this applies to all sections.  
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-{{:vivado:mig_51.jpg|}} 
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-Back in the Project Explorer, double click and open "helloworld.c" under the "src" folder. "src" stands for source.  
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-This is the main .C file which will print "hello world" in the console when executed.  
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-{{:vivado:mig_52.jpg|}} 
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-Under the "Search" tab on the main tool bar, you will find a symbol with a red arrow and three green square boxes. Click on this to open the Program FPGA window.  
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-Make sure that the Hardware Platform is targeted at "design_1_wrapper_hw_platform_0".  
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-In the software configuration box, under ELF File to Initialize in Block RAM, the option must read "bootloop". 
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-Now click on Program.  
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-{{:vivado:mig_53.jpg|}} 
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-After the FPGA has been successfully programmed with the .bit file we have generated in Vivado, right click on the "display_hello_world" main project folder which has been highlighted in the screen capture below.  
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-At the bottom of the list, select Run Configurations. The RUn Configuration window will open. This window is divided into two main sections. In the left panel, under Xilinx C/C++ application(GDB), select display_hello_world.elf. 
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-On the right side of this window, you will see five main tabs. Select the STDIO Connection tab.  
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-{{:vivado:mig_54.jpg|}} 
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-{{:vivado:mig_55.jpg|}}