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nexys4-ddr:migration_n4 [2022/09/12 15:13] – changed forum.digilentinc.com to forum.digilent.com jeff.greenberg_ni.comnexys4-ddr:migration_n4 [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 +====== Nexys4-DDR Migration Guide: Nexys4 ======
  
 +===== Introduction =====
 +
 +This guide describes how to migrate an ISE or EDK project that targeted the Nexys4 board to the Nexys4-DDR.
 +
 +===== Step 1: Modifying the constraints =====
 +
 +You will need to update the pin constraints of your design. Open up your UCF file and the Nexys4-DDR Master UCF file (Available [[nexys4-ddr:start|here]]) and replace the constraints in your file with those found in the Master UCF. For example, say you have LD0 on the Nexys4 constrained as follows:
 +
 +<code>
 +NET "myled"         LOC=T8 | IOSTANDARD=LVCMOS33;
 +</code>
 +
 +And the Nexys4-DDR UCF has this constraint for LD0:
 +
 +<code>
 +#NET "led<0>"         LOC=H17 | IOSTANDARD=LVCMOS33; #IO_L18P_T2_A24_15
 +</code>
 +
 +Then you should replace the constraint in your UCF with the constraint from the Nexys4-DDR Master UCF. Then replace the NET name with the name of your top level port and uncomment it:
 +
 +<code>
 +NET "myled"         LOC=H17 | IOSTANDARD=LVCMOS33; #IO_L18P_T2_A24_15
 +</code>
 +
 +You will need to do this for each top level port in your design. If it is not clear what pin for a particular component on the Nexys4 corresponds to the what pin on the Nexys4-DDR, try looking for your component in the next section to see if that clears things up.
 +
 +===== Step 2: Components that require additional changes =====
 +
 +Some hardware changes have been made to the Nexys4-DDR design that will affect how you interact with some components. If your Nexys4 design uses any of the components below, you will need to read what changes you will have to make in order for the design to work on the Nexys4-DDR.
 +
 +==== CellRAM ====
 +
 +The Nexys4-DDR no longer has CellRAM, it has been replaced by 128 MB of DDR2. If you have a non-microblaze design that used the CellRAM, then you can use the "SRAM to DDR" component as an adapter between your design and the DDR2. This component is described [[nexys4-ddr:sram|here]]. This component does not support synchronous burst accesses like the CellRAM did, so if you need high bandwidth accesses, you will need to directly instantiate the Memory Interface Generator (MIG) in your design. Files that properly configure the MIG to work with the memory on the Nexys4-DDR are available in the "Design Resources" section [[nexys4-ddr:start|here]].
 +
 +If you have a microblaze design that used either the External Memory Controller (EMC) core or a custom Digilent made memory controller core, then you should remove it and replace it with the MIG. This will greatly increase the performance of your Microblaze system. Use the files mentioned above to properly configure the MIG.
 +
 +===== Still Stuck? =====
 +
 +If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilent.com/|Digilent Forum]], and we will do our best to get your design up and running.