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| nexys4-ddr:migration_n2 [2017/09/14 00:28] – [EDK Projects] sbobrowicz | nexys4-ddr:migration_n2 [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ==== ISE Projects ==== | ==== ISE Projects ==== | ||
| - | This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https:// | + | This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https:// |
| ==== EDK Projects ==== | ==== EDK Projects ==== | ||
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| ==== Instantiated FPGA Resources ==== | ==== Instantiated FPGA Resources ==== | ||
| - | Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[http:// | + | Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[https:// |
| ==== FX/2 Connector ==== | ==== FX/2 Connector ==== | ||
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| ===== Still Stuck? ===== | ===== Still Stuck? ===== | ||
| - | If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https:// | + | If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https:// |