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nexys4-ddr:migration_n2 [2015/03/14 05:46] – sbobrowicznexys4-ddr:migration_n2 [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Nexys4-DDR Migration Guide: Nexys2 ====== ====== Nexys4-DDR Migration Guide: Nexys2 ======
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-=====!*!*UNDER CONSTRUCTION*!*!=====  
  
 ===== Introduction ===== ===== Introduction =====
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 ==== ISE Projects ==== ==== ISE Projects ====
  
-This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilentinc.com/|Digilent Forum]].+This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilent.com/|Digilent Forum]].
  
 ==== EDK Projects ==== ==== EDK Projects ====
  
-Since Spartan3E designs could only be created as PLB projects, your design will need to be redesigned with equivalent AXI versions of the PLB cores. This is because Xilinx does not support the PLB bus in 7-series devices. The easiest way to do this is to start with an AXI project that already has most of the components properly connected, and then to just remove the ones you don't need, and add any additional cores that were in your design. You may use this project for that purpose: +Since Spartan3E designs could only be created as PLB projects, your design will need to be redesigned with equivalent AXI versions of the PLB cores. This is because Xilinx does not support the PLB bus in 7-series devices. This will likely require that you create a new project from scratch in EDK with equivalent functionality. 
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-FIXME -- Add project+
  
-That project has the DDR2, ethernet, and nearly all of the other peripherals properly connected to the AXI versions of the cores. Its original purpose was for our Manufacturing test, so the net names may be confusing. If you choose to follow this method, you can skip to step 3. Note you will only need to modify the constraints of any cores you manually add: the constraints that are currently in the project are all correct for the Nexys4-DDR.+Due to the maturity of the EDK toolset, Digilent no longer provides support for its use. If you would like assistance from Digilent, it is recommended to instead migrate your design into the Vivado toolset. Many example projects and tutorials are available on the Nexys 4 DDR Resource Center that can help you become acquainted with Vivado.
  
 ===== Step 2: Target the Nexys4-DDR FPGA ===== ===== Step 2: Target the Nexys4-DDR FPGA =====
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 ==== Instantiated FPGA Resources ==== ==== Instantiated FPGA Resources ====
  
-Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf|7 Series Libraries Guide.]] +Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[https://www.xilinx.com/htmldocs/xilinx14_7/7series_hdl.pdf|7 Series Libraries Guide.]] 
  
 ==== FX/2 Connector ==== ==== FX/2 Connector ====
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 ===== Still Stuck? ===== ===== Still Stuck? =====
  
-If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilentinc.com/|Digilent Forum]], and we will do are best to get your design up and running.+If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilent.com/|Digilent Forum]], and we will do our best to get your design up and running.