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nexys4-ddr:migration_n2 [2015/03/14 05:02] – sbobrowicznexys4-ddr:migration_n2 [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Nexys4-DDR Migration Guide: Nexys2 ====== ====== Nexys4-DDR Migration Guide: Nexys2 ======
- 
-=====!*!*UNDER CONSTRUCTION*!*!=====  
  
 ===== Introduction ===== ===== Introduction =====
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 ==== ISE Projects ==== ==== ISE Projects ====
  
-This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilentinc.com/|Digilent Forum]].+This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilent.com/|Digilent Forum]].
  
 ==== EDK Projects ==== ==== EDK Projects ====
  
-FIXME -- Forgot about the fact that all Nexys2 designs will use the PLB+Since Spartan3E designs could only be created as PLB projects, your design will need to be redesigned with equivalent AXI versions of the PLB cores. This is because Xilinx does not support the PLB bus in 7-series devices. This will likely require that you create a new project from scratch in EDK with equivalent functionality. 
  
-Open the Project in Xilinx Platform Studio. Allow the tools to upgrade any IP that it says is safe to upgrade. If the project is too old, it is possible that the version of an IP core you have used is no longer present in 14.7. If this is the case, you may have to upgrade the project to an earlier version that still contains the core before upgrading to 14.7. For example, if your project was created in 13.3, you may need to open it up and upgrade it in 14.2, and then open it again in 14.7. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilentinc.com/|Digilent Forum]].+Due to the maturity of the EDK toolset, Digilent no longer provides support for its use. If you would like assistance from Digilent, it is recommended to instead migrate your design into the Vivado toolset. Many example projects and tutorials are available on the Nexys 4 DDR Resource Center that can help you become acquainted with Vivado.
  
 ===== Step 2: Target the Nexys4-DDR FPGA ===== ===== Step 2: Target the Nexys4-DDR FPGA =====
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 ==== Instantiated FPGA Resources ==== ==== Instantiated FPGA Resources ====
  
-Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf|7 Series Libraries Guide.]] +Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[https://www.xilinx.com/htmldocs/xilinx14_7/7series_hdl.pdf|7 Series Libraries Guide.]] 
  
 ==== FX/2 Connector ==== ==== FX/2 Connector ====
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 ==== CellRAM ==== ==== CellRAM ====
  
-The Nexys4-DDR no longer has CellRAM, it has been replaced by 128 MB of DDR2. If you have a non-microblaze design that used the CellRAM, then you can use the "SRAM to DDR" component as an adapter between your design and the DDR2. This component is described [[nexys4-ddr:sram|here]]. This component does not support synchronous burst accesses like the CellRAM did, so if you need high bandwidth accesses, you will need to directly intantiate the Memory Interface Generator (MIG) in your design. Files that properly configure the MIG to work with the memory on the Nexys4-DDR are available in the "Design Resources" section [[nexys4-ddr:start|here]].+The Nexys4-DDR no longer has CellRAM, it has been replaced by 128 MB of DDR2. If you have a non-microblaze design that used the CellRAM, then you can use the "SRAM to DDR" component as an adapter between your design and the DDR2. This component is described [[nexys4-ddr:sram|here]]. This component does not support synchronous burst accesses like the CellRAM did, so if you need high bandwidth accesses, you will need to directly instantiate the Memory Interface Generator (MIG) in your design. Files that properly configure the MIG to work with the memory on the Nexys4-DDR are available in the "Design Resources" section [[nexys4-ddr:start|here]].
  
 If you have a microblaze design that used either the External Memory Controller (EMC) core or a custom Digilent made memory controller core, then you should remove it and replace it with the MIG. This will greatly increase the performance of your Microblaze system. Use the files mentioned above to properly configure the MIG. If you have a microblaze design that used either the External Memory Controller (EMC) core or a custom Digilent made memory controller core, then you should remove it and replace it with the MIG. This will greatly increase the performance of your Microblaze system. Use the files mentioned above to properly configure the MIG.
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 ===== Still Stuck? ===== ===== Still Stuck? =====
  
-If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilentinc.com/|Digilent Forum]], and we will do are best to get your design up and running.+If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilent.com/|Digilent Forum]], and we will do our best to get your design up and running.