Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
nexys4-ddr:gsg [2015/01/15 23:14] – Jesse Njugunanexys4-ddr:gsg [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 7: Line 7:
 To power on the Nexys4DDR, you will need a micro-USB cable. Plug this cable into the JTAG slot on the Nexys4DDR, plug the other end into your computer, and flip the power switch to the "On" position. This will begin the out of box demo. To power on the Nexys4DDR, you will need a micro-USB cable. Plug this cable into the JTAG slot on the Nexys4DDR, plug the other end into your computer, and flip the power switch to the "On" position. This will begin the out of box demo.
  
-More information on this startup demo can be found FIXME.+More information on this startup demo can be found [[nexys4-ddr:userdemo|here]].
 ----- -----
 =====Getting Started with Vivado===== =====Getting Started with Vivado=====
  
-The files needed for this demo can be downloaded by clicking {{:nexys4-ddr:abacus_verilog_srcfiles.zip|here}}.  You'll also need the constraints file. The constraint file is dependent on the development environment. For ISE designs the UCF file can be downloaded [[http://digilentinc.com/Data/Products/NEXYS4DDR/Nexys4DDR_Master_ucf.zip|here]]. For Vivado designs, the XDC file can be downloaded [[http://digilentinc.com/Data/Products/NEXYS4DDR/Nexys4DDR_Master_xdc.zip|here]].+The files needed for this demo can be downloaded by clicking {{:nexys4-ddr:abacus_verilog_srcfiles.zip|here}}.  You'll also need the constraints file. The constraint file is dependent on the development environment. For ISE designs the UCF file can be downloaded {{:nexys4-ddr:nexys4ddr_master_ucf.zip|here}}. For Vivado designs, the XDC file can be downloaded {{:nexys4-ddr:nexys4ddr_master_xdc.zip|here}}.
  
 More information on the Abacus project can be found [[basys3:abacus|here]]. More information on the Abacus project can be found [[basys3:abacus|here]].
Line 42: Line 42:
 {{ :basys3:3.png?nolink&500 |}} {{ :basys3:3.png?nolink&500 |}}
  
-This is where we'll import our Xlilinx Design Constraints file (XDC) to map the HDL signals to the Artix-7 pins. Click on "Add Files", navigate to where you saved your [[http://digilentinc.com/Data/Products/NEXYS4DDR/Nexys4DDR_Master_xdc.zip|Nexys4DDR_Master.xdc]] file, select it, and click "Next".+This is where we'll import our Xlilinx Design Constraints file (XDC) to map the HDL signals to the Artix-7 pins. Click on "Add Files", navigate to where you saved your {{:nexys4-ddr:nexys4ddr_master_xdc.zip|Nexys4DDR_Master.xdc}} file, select it, and click "Next".
 {{ :nexys:nexys4:1.png?nolink&500 |}} {{ :nexys:nexys4:1.png?nolink&500 |}}
  
Line 62: Line 62:
  
 ----- -----
- 
 ====Working with Vivado==== ====Working with Vivado====
 FIXME FIXME