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nexys4-ddr:advmb [2015/01/16 00:01] – created Varun Kondagunturinexys4-ddr:advmb [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Advanced Microblaze Design using Memory Interface Generator (MIG), Ethernet, UART & GPIOs ====== ====== Advanced Microblaze Design using Memory Interface Generator (MIG), Ethernet, UART & GPIOs ======
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 +=====!*!*UNDER CONSTRUCTION*!*!=====  
 +This page is currently under development and may not be a complete demo at this time. This notice will be removed once the tutorial is in a stable state 
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 ===== Description ===== ===== Description =====
-This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the Getting Started with Microblaze Wiki ([[nexys4-ddr:gsmb|Getting Started with Microblaze]]) guide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 DDR FPGA board. +This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the [nexys4-ddr:gsmb|Getting Started with Microblaze]] guide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 DDR FPGA board. 
  
  
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 {{:vivado:mig_13.jpg|}}  {{:vivado:mig_13.jpg|}} 
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-Select the **Clocking Options** tab. 
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-Under Input Clock Information Section, for the Primary clock, select //Single ended clock capable pin// as the source 
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-{{:vivado:clk_single_step13.jpg|}} 
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 14. Select the **Output Clocks** tab. 14. Select the **Output Clocks** tab.