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nexys:nexysvideo:refmanual [2015/05/06 20:06] – [Quad-SPI Flash] Joshua Woldstadnexys:nexysvideo:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-====== **UNDER CONSTRUCTION** ======+Wrong Namespace, don't edit this! 
  
-This wiki page is currently under construction, everything on this page is liable to change.  +Go to [[nexys-video:refmanual|here]]
-Placeholders are also included on this page. +
- +
----- +
- +
- +
-====== Overview ====== +
- +
-{{ :nexys:nexysvideo:nexysvideooblique.png?400|}} +
- +
-The Nexys Video board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity FPGA (Xilinx part number XC7A200T-1SBG484C) – the largest Artix-7 die at the time of writing, generous external memories, high-speed digital video ports, and 24-bit audio codec, make the Nexys Video is perfectly suited for audio and video processing appllications. Several built-in peripherals, including Ethernet, USB-UART, and a high bandwidth USB data transfer protocol expand the connectivity of the Nexys Video so that it can cleanly be integrated as a single component of large system. The Nexys Video also includes provisions for direct human interaction with a connector for USB-HID devices, an OLED Display, and a vast assortment of switches, buttons and LEDs. Lastly, the FMC and Pmod Connectors can be used to add virtually any functionality or connection interface your application demands. +
- +
- +
-The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. Artix-7 200T features include:   +
- +
-  * 33,650 logic slices, each with four 6-input LUTs and 8 flip-flops +
-  * Close to 13 Mbits of fast block RAM (3x more than the Nexys 4 DDR) +
-  * Ten clock management tiles, each with phase-locked loop (PLL)  +
-  * 740 DSP Slices +
-  * Internal clock speeds exceeding 450MHz +
-  * On-chip analog-to-digital converter (XADC) +
- +
-The Nexys Video also offers an improved collection of ports and peripherals, including:  +
-  * 8 user switches +
-  * 8 user LEDs  +
-  * 128x32 monochrome OLED display +
-  * USB-UART Bridge  +
-  * 160-pin FMC LPC connector  +
-  * Micro SD card connector +
-  * HDMI Sink and HDMI Source  +
-  * DisplayPort Source  +
-  * Audio codec w/ four 3.5mm jacks +
-  * 6 user push buttons  +
-  * User EEPROM  +
-  * 10/100/1000 Ethernet PHY +
-  * 512MiB 800Mt/s DDR3  +
-  * Serial Flash  +
-  * Four Pmod ports +
-  * Pmod for XADC signals  +
-  * Digilent Adept USB port for programming and data  +
-  * USB HID Host for mice, keyboards and USB MSD Host  +
- +
- +
-In addition to being compatible with Xilinx’s ISE toolset, The Nexys Video also works with Xilinx’s the new high-performance Vivado  ® Design Suite. It is supported under the free “Webpack” license, so designs can be implemented at no additional cost. This free license now includes the ability to create Microblaze soft-core processor designs (in Vivado only), which greatly reduces the time needed to implement complex systems.  Design resources and example projects are available for download at the Nexys Video Resource Center, accessible from reference.digilentinc.com. +
- +
- +
-{{ :nexys:nexysvideo:diagram.png?400 |}}  +
- +
-| **Callout**  | **Component Description**                 | **Callout**  | **Component Description**             | +
-|** 1**            | Power select jumper and battery header    | **13**           | FPGA configuration reset button       | +
-| **2**            | Adept USB (JTAG and UART)                 | **14**           | CPU reset button (for soft cores)     | +
-| **3**            | External configuration jumper (SD / USB)  | **15**           | Analog signal Pmod connector (XADC)   | +
-| **4**            | Pmod connector(s)                         | **16**           | Programming mode jumper               | +
-|** 5**            | Microphone                                | **17**           | Audio connector                       | +
-| **6**            | Power supply test point(s)                | **18**           | VGA connector                         | +
-| **7**            | LEDs (16)                                 | **19**           | FPGA programming done LED             | +
-| **8**            | Slide switches                            | **20**           | Ethernet connector                    | +
-| **9**            | Eight digit 7-seg display                 | **21**           | USB host connector                    | +
-| **10**           | JTAG port for (optional) external cable   | **22**           | PIC24 programming port (factory use)  | +
-| **11**           | Five pushbuttons                          | **23**           | Power switch                          | +
-| **12**           | Temperature sensor                        | **24**           | Power jack                            | +
- +
- +
----- +
- +
- +
-====== Power Supplies ====== +
- +
-The Nexys Video board can receive power from an external power supply through the center-positive barrel jack (J21) or the two-pin battery header (J22). The external supply voltage must be 12 V ±5 %. The Nexys Video cannot be powered from the USB bus.  +
- +
-All Nexys Video power supplies can be turned on and off by a single logic-level power switch (SW8). Enables of power supplies not connected directly to the power switch are disabled indirectly. A power-good LED (LD16), driven by the “power good” output of the on-board regulators, indicates that the supplies are turned on and operating normally. An overview of the Nexys Video power circuit is shown in Figure 1.  +
- +
-{{:nexys:nexysvideo:powercircuit.png?400|}} +
- +
- +
-//Figure 1. Nexys Video power circuit// +
- +
- +
-An external power supply can be used by plugging it into the power jack (J21).  The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 12VDC ±5 %. The minimum current rating of the supply depends on the actual design implemented in the FPGA, but at least 3A of current (i.e., at least 36W of power) is recommended. +
- +
- +
-Instead of a wall supply an external battery pack can be used by connecting the battery’s positive terminal to the positive pin of J22 and the negative terminal to the negative pin. Incorrect polarity might cause permanent damage to the board. To power the Nexys Video and any peripheral other than an FMC mezzanine card using the 12P0V supply, the battery voltage must be in the 6-15 V range. Since the external power supply pin is wired directly to the 12P0V pin of the FMC connector, in FMC applications the battery voltage must be 12VDC ±5 %, the same as the wall supply specification. In any case, 15 V is an absolute maximum. +
- +
- +
-Voltage regulator circuits from Analog Devices create the different voltages required by the FPGA and on-board peripherals from the main power input. Some regulators use the outputs of another regulator as input, depending on design considerations. In some cases this chaining helps in creating the proper power-on sequence for circuits. In other cases the chaining of power supply enables achieves the same purpose. +
- +
- +
-Table 1 provides information on maximum and typical currents for each power rail. The typical currents strongly depend on FPGA configuration and the values provided are typical of medium size/speed designs. +
- +
-| **Supply**        | **Circuits**                                                             | **Device**     | **Current (max/typical)**  | +
-| 3.3 V             | FPGA I/O, USB, FMC, Clocks, Pmod, Ethernet, SD slot, Flash, DisplayPort  | IC26: ADP5052  | 4A / 0.1 to 1.5A           | +
-| 1.0 V             | FPGA Core                                                                | IC26: ADP5052  | 4A / 0.2 to 2A             | +
-| 1.8 V             | FPGA Auxiliary                                                           | IC26: ADP5052  | 1.2A / 0.15A               | +
-| 1.5 V             | DDR3 and FPGA I/O                                                        | IC26: ADP5052  | 1.2 A / 0.5 A              | +
-| 2.5 V             | FPGA I/O and Ethernet                                                    | IC26: ADP5052  | 0.2 A / 0.1 A              | +
-| VADJ (1.2-3.3 V)  | User I/O, FMC and FPGA I/O                                               | IC28: ADP2384  | 2 A / 0.1 A                | +
-| 3.3 V             | Audio analog supply                                                      | IC6: ADP150    | 0.15 A / 0.05 A            | +
-| 5.0 V             | USB Host, HDMI                                                           | IC30: ADP2370  | 0.8 A / 0.5 A              | +
-| MGT 1.0 V         | Gigabit Transceivers VCC                                                 | IC31: ADP123   | 0.3 A                      | +
-| MGT 1.2 V         | Gigabit Transceivers VTT                                                 | IC33: ADP123   | 0.3 A                      | +
-| XADC 1.8 V        | XADC supply                                                              | IC34: ADP123   | 0.3 A                      | +
-//Table 1. Voltage rail power ratings// +
- +
- +
-The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine connector, user push-buttons, switches, XADC Pmod connector and the FPGA banks connected to these peripherals (banks 15, 16). The feedback pin of the VADJ regulator is connected to an analog multiplexer controlled by two FPGA signals, “SET_VADJ(1:0)”. The multiplexer is able to change the resistor values in the feedback loop, thereby changing the voltage on the regulator’s output. Depending on the value set on the “SET_VADJ(1:0)” pins, the possible voltages are listed in Table 2. The third control pin is the “VADJ_EN” signal, which can disable the regulator altogether. If these control pins are not used in the FPGA design, on-board pull resistors enable the regulator and set the VADJ voltage to 1.2 V. +
- +
-An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care must be taken to disable the regulator first by bringing “VADJ_EN” low, setting “SET_VADJ(1:0)” and enabling the regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these signals. +
- +
- +
-| **SET_VADJ(1:0)**  | **VADJ**  | +
-| 00 (default)       | 1.2 V     | +
-| 01                 | 1.8 V     | +
-| 10                 | 2.5 V     | +
-| 11                 | 3.3 V     | +
- +
-//Table 2. VADJ programmable voltages// +
- +
- +
-====== FPGA Configuration ====== +
- +
-After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways: +
- +
-  - A PC can use the Digilent USB-JTAG circuitry (port 12, labeled “PROG”) to program the FPGA any time the power is on. +
-  - A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA.  +
-  - A programming file can be transferred to the FPGA from a micro SD card. +
-  - A programming file can be transferred from a USB mass-storage device (ex. pen drive) attached to the USB HID port. +
- +
-Figure 2 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP4) and a media selection jumper (JP3) select between the programming modes. +
- +
-{{:nexys:nexysvideo:configoptions.png?400|}} +
- +
-Figure 2. Nexys Video Configuration Options +
- +
-The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs).  +
- +
-Bitstreams are stored in volatile SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port. +
- +
-An Artix-7 200T bitstream is typically 77,845,216 bits and can take a long time to transfer depending on the programming mode. The time it takes to program the Nexys Video can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used. This option is available for all programming modes. +
- +
-Mode-specific speed-ups are also available. JTAG clock frequency can be set to the maximum supported by the programming cable in iMPACT/Vivado Hardware Manager. Similarly, the clock frequency for the SPI Flash can be increased in device properties (Vivado) or bitstream generation options (ISE). The micro-SD and USB mass-storage device configuration modes already operate at their maximum possible speed. +
- +
-After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG” button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from whatever method has been selected by the programming mode jumpers. +
- +
-The following sections provide greater detail about programming the Nexys Video using the different methods available. +
- +
-===== 2.1 JTAG Programming ===== +
- +
-The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J12) or an external JTAG programmer, such as the Digilent JTAG HS3, attached to port J17. You can perform JTAG programming at any time after the Nexys Video has been powered on, regardless of what the mode jumper (JP4) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs. +
- +
-Programming the Nexys Video with an uncompressed bitstream using the on-board USB_JTAG circuitry usually takes around four seconds with a 30MHz JTAG clock. +
- +
-JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the labtools version of Vivado.  +
- +
-The demonstration project available at digilentinc.com gives an in depth tutorials on how to program your board.   +
- +
-===== 2.2 Quad-SPI Programming ===== +
- +
-For the FPGA to be able to configure itself from the SPI Flash, it first needs to be programmed with the bitstream. This is called indirect programming and is a two-step process controlled by Hardware Manager (Vivado) or iMPACT (ISE). First, the FPGA is programmed with a design that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting. Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events. +
- +
-Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written however, FPGA configuration can be very fast, less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilnx tools that can affect configuration speed. The on-board flash has a Quad-SPI interface, which supports single (x1), dual (x2) and quad (x4) modes. The quad mode results in the fastest possible data transfer rate. For it to work, the bitstream needs to be generated with the x4 bus width option (Vivado device property) and the non-volatile quad configuration bit in the flash to be enabled. The Nexys Video is shipped with this bit enabled. +
- +
-Indirect programming of the flash can be done using the iMPACT tool included with ISE or Hardware Manager of Vivado. The correct part to be set in the tools is s25fl256xxxxxx0 from the manufacturer Spansion. +
- +
- +
-===== 2.3 USB Host and Micro SD Programming ===== +
- +
-You can program the FPGA from a pen drive attached to the USB-HID port (J15) or a microSD card inserted into J3 by doing the following:   +
-  - Format the storage device (pen drive or microSD card) with a FAT32 file system. +
-  - Place a single .bit configuration file in the root directory of the storage device. +
-  - Attach the storage device to the Nexys Video. +
-  - Set the JP4 Programming Mode jumper on the Nexys Video to “USB/SD”. +
-  - Select the desired storage device using JP3. +
-  - Push the PROG button or power-cycle the Nexys Video. +
- +
-The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Artix-7 device will be rejected by the FPGA. +
- +
-The Auxiliary Function Status or “BUSY” LED (LD14) gives visual feedback on the state of the configuration process when the FPGA is not yet programmed: +
- +
-  * When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration medium (microSD or pen drive) and downloading a bitstream to the FPGA. +
-  * A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in. +
-  * In case of an error during configuration the LED will blink rapidly. It could  be that the device plugged in is not getting recognized, it is not properly formatted or the bitstream is not compatible with the FPGA. +
- +
-When the FPGA is has been successfully configured, the behavior of the LED is application-specific. For example, if a USB keyboard is plugged in, a rapid short blink will signal the receipt of an HID input report from the keyboard. +
- +
----- +
- +
-====== Memory ====== +
- +
-The Nexys Video board contains two external memories: a 512MiByte volatile DDR3 memory and a 32MiByte non-volatile serial Flash device. The DDR3 uses a 16-bit wide memory component soldered on the board with industry-standard interface. The serial Flash is on a dedicated quad-mode (x4) SPI bus. +
- +
----- +
- +
- +
-====== DDR3 ====== +
- +
-The Nexys Video includes one Micron MT41K256M16HA-187E DDR3 memory component creating a single rank, 16-bit wide interface. It is routed to a 1.5V-powered HR (High Range) FPGA bank with 50 ohm controlled single-ended trace impedance. 50 ohm internal terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side on-die terminations (ODT) are used for impedance matching. +
- +
-For proper operation of the memory a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard hides away the complexities of a DDR3 interface. Depending on the tool used (ISE, EDK or Vivado) the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of several DDR3 parameters optimized for the particular application. Table 2 below lists the MIG Wizard settings optimized for the Nexys Video. +
- +
-| **Setting**                         | **Value**                   | +
-| Memory type                         | DDR3 SDRAM                  | +
-| Max. clock period                   | 2500ps (800Mbps data rate)  | +
-| Clock ratio                         | 4:1                         | +
-| Memory type                         | Components                  | +
-| Memory part                         | MT41K256M16HA-125           | +
-| Memory voltage                      | 1.5V                        | +
-| Data width                          | 16                          | +
-| Data mask                           | Enabled                     | +
-| Input clock period                  | 10000ps (100 MHz)           | +
-| Output driver impedance             | RZQ/6                       | +
-| Chip Select pin                     | Disabled                    | +
-| Rtt (nominal) – On-die termination  | RZQ/6                       | +
-| Internal Vref                       | Enabled                     | +
-| Internal termination impedance      | 50ohms                      | +
-Table 3 DDR3 Settings for the Nexys Video +
- +
- +
-The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC  file is provided on the Digilent website to speed up the process. +
- +
-For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)¹. +
- +
----- +
- +
- +
-====== Quad-SPI Flash ====== +
- +
-Non-volatile storage is provided by a Spansion S25FL256S flash memory. FPGA configuration files can be written to it, and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 200T configuration file requires just over 9 MiB (mebibyte) of memory, leaving about 70% of the flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data. +
- +
-The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. +
- +
-**NOTE: Refer to the manufacturer’s data sheets² and Xilinx user guides³ for more information.** +
- +
-{{:nexys:nexysvideo:pinout.png?400|}} +
- +
-Figure 3. Nexys Video SPI Flash pin-out +
- +
- +
- ¹[[http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf|http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf]] +
- ²[[http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf|http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf]] +
- ³[[http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf|http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf]] +
- +
- +
----- +
- +
- +
-====== 4 Ethernet PHY====== +
- +
-The Nexys Video board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and MDIO for management. Bank 13 powered at 2.5V is populated with these signals. The auxiliary interrupt (INT_B), power management (PME_B) signals are also wired to bank 13. The reset signal (RST_B) is the only one wired to a different bank (34), powered at 3.3V. The connection diagram can be seen on Figure 4. +
- +
-At power-on reset, the PHY is set to the following defaults using the configuration pins in parenthesis: +
- +
-  * Auto-negotiation enabled, advertising all 10/100/1000 modes (AN[1:0]) +
-  * PHY address=00001 (PHY_AD[2:0]) +
-  * No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY) +
- +
-If an Ethernet cable is plugged in, establishing link is attempted straight after power-up, even if the FPGA is not programmed. +
- +
-Three status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD10) and valid link state (LD9). The table below shows the default behavior. +
- +
-| **Function**  | **Designator**  | **State**                 | **Description**                                | +
-| **ACT**       | LD10            | Blinking                  | Transmitting or receiving                      | +
-| **LINK**      | LD9             | Blinking                  | Transmitting or receiving                      | +
-| :::           | :::             | On                        | Link up                                        | +
-| **USER**      | LD8             | Blinking 0.4s ON, 2s OFF  | Link up, Energy Efficient Ethernet (EEE) mode  | +
-| :::           | :::             | On                        | Link up, no traffic                            | +
-| :::           | :::             | Off                       | Link down                                      | +
- +
-Table 4. Ethernet status LEDs +
- +
-The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium and the media access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY’s RGMII interface. Vivado-based design can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wire it to the processor and the memory subsystem. At the time of writing the IP core needed to be licensed separately. +
- +
-On an Ethernet network each node needs a unique MAC address. To this end a Microchip 24AA025E48 EEPROM is provided on the Nexys Video. On one hand it is a read-writeable EEPROM that can be accessed via I²C. On the other hand it features a read-only memory section that comes pre-programmed with a unique identifier. This unique identifier can be read and used as a MAC address, avoiding a possible address conflict on the network. The device address of the EEPROM is 1010000b. The out-of-box Ethernet demo uses the unique MAC to allow connecting several Nexys Video boards to the same network. +
- +
-A downloadable demonstration project can be found on the Nexys  Video product page at [[http://www.digilentinc.com|www.digilentinc.com]]. +
- +
-{{ :nexys:nexysvideo:pinconnect.png?500 |}} +
- +
-Figure 4. Pin connections between the Artix-7 and the Ethernet PHY +
- +
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- +
-====== 5 Oscillators/Clocks ====== +
- +
-The Nexys Video board includes a single 100MHz crystal oscillator connected to pin R4 (R4 is a MRCC input on bank 34). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 100MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” (ug472¹) available from Xilinx. +
-Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or Core Generator tools. +
- +
-¹[[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf |http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf ]] +
- +
- +
----- +
- +
- +
-====== 6 USB UART Bridge (Serial Port) ====== +
- +
-The Nexys Video includes an FTDI FT232R USB-UART bridge (attached to connector J13) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from Windows Update or www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the V18 and AA19 FPGA pins. +
- +
-Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD13) and the receive LED (LD12). **Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.** +
- +
-The connections between the FT232R and the Artix-7 are shown in Figure 5. +
- +
-{{:nexys:nexysvideo:videoconnections.png?400|}}+