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nexys:nexysvideo:gsmbs [2015/06/02 20:18] – Thomas Kappenmannexys:nexysvideo:gsmbs [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Getting Started with Microblaze Servers ====== ====== Getting Started with Microblaze Servers ======
------+**Note:**The Nexys Video uses a Gigabit Ethernet module which requires the TEMAC IP that is **not contained in the Vivado Webpack**. In order to complete this tutorial, you must either purchase a license for the TEMAC IP or get the evaluation license for free from their website by following [[vivado:temac|this guide]]. 
 + 
  
 ===== Description ===== ===== Description =====
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   * Xilinx Vivado with the SDK package.    * Xilinx Vivado with the SDK package. 
     * Follow this Wiki guide ([[vivado:installation|Installing Vivado]] ) on how to install and activate Vivado 2014.4     * Follow this Wiki guide ([[vivado:installation|Installing Vivado]] ) on how to install and activate Vivado 2014.4
 +  * TEMAC IP license installed 
 +    * Follow this Wiki guide ([[vivado:temac|Installing the 120 Day Evaluation License for the TEMAC IP]]).
  
 ==== Board Support Files ==== ==== Board Support Files ====
   * Board Support Files. These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.    * Board Support Files. These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks. 
-    * Follow this Wiki guide ([[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]  ) on how to install Board Support Files for Vivado 2014.4 **The Nexys Video board files can be found {{:NexysVideo.zip|here}}**+    * Follow this Wiki guide ([[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]  ) on how to install Board Support Files for Vivado 2014.4. 
 +**The Nexys Video {{https://github.com/Digilent/vivado-boards/tree/master/new/board_files/nexys_video/A.0|board files}}**
  
  
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 7. Click "Run Block Automation" circled in blue, and change the options to match the ones in the picture below. Click "Ok". 7. Click "Run Block Automation" circled in blue, and change the options to match the ones in the picture below. Click "Ok".
  
-{{:nexys4-ddr:server_3.jpg?nolink|}}+{{:nexys:nexysvideo:4.jpg?nolink|}}
  
 ==== Adding the Necessary Output Clocks ==== ==== Adding the Necessary Output Clocks ====
  
-8. Double-click the Clocking Wizard block highlighted below, and set CLK_IN1 to use "sys_clock" and EXT_RESET_IN to use "reset".+8. Double-click the //Clocking Wizard// block highlighted below, and set CLK_IN1 to use "sys_clock" and EXT_RESET_IN to use "reset".
  
 {{:nexys4-ddr:server_4.jpg?nolink|}} {{:nexys4-ddr:server_4.jpg?nolink|}}
  
-9. Select the Output Clocks tab and enable //clk_out2//, //clk_out3//, and //clk_out4//. Set //clk_out2// to **166,667MHz**, //clk_out3// to **200MHz**, and  //clk_out4// to **25MHz**. Set the Reset Type to **Active Low** using the bullets below. When you are finished, click Ok.+9. Select the Output Clocks tab and enable //clk_out2//, //clk_out3//. Set //clk_out2// to **200MHz**, and //clk_out3// to **125MHz**. Set the Reset Type to **Active Low** using the bullets below. When you are finished, click Ok.
  
-{{:arty:3.jpg?nolink|}}+{{:nexys:nexysvideo:6.jpg?nolink|}}
  
-Your block design should look something like this:+==== Adding More Interrupts ====
  
-{{:arty:5.jpg?nolink|}}+10. Find the //Concat// block and double click it. Set number of ports to 5 and press OK. 
 + 
 +{{:nexys:nexysvideo:5.jpg?nolink|}}
  
 ==== Adding the IP Cores ==== ==== Adding the IP Cores ====
  
-10. We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:+11. We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:
   * Memory Interface Generator   * Memory Interface Generator
   * AXI Uartlite   * AXI Uartlite
-  * AXI EthernetLite+  * AXI Ethernet Subsystem
   * AXI Timer   * AXI Timer
  
 Add all of these to your design, one at a time, using the //"Add IP"// button. Once they are all added, you should see the four blocks shown below. Add all of these to your design, one at a time, using the //"Add IP"// button. Once they are all added, you should see the four blocks shown below.
  
-{{:arty:2.jpg?nolink|}}+{{:nexys:nexysvideo:7.jpg?nolink|}}
  
 ==== Configuring and Routing the IP Cores ==== ==== Configuring and Routing the IP Cores ====
  
-11. Click //"Run Block Automation"// and run it for the mig_7series_0 block.+12. Click //"Run Block Automation"// and run it for the **mig_7series_0** block.
  
-{{:nexys4-ddr:server_8.jpg?nolink|}}+{{:nexys:nexysvideo:8.jpg?nolink|}}
  
 When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys Video. Click OK to dismiss this message. You will find the MIG IP block now has additional input and output pins which have to be connected to valid signals. When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys Video. Click OK to dismiss this message. You will find the MIG IP block now has additional input and output pins which have to be connected to valid signals.
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 {{:nexys4-ddr:mig_27-2.jpg?nolink|}} {{:nexys4-ddr:mig_27-2.jpg?nolink|}}
  
-12. +13. Click //"Run Block Automation"// and run it for the **axi_ethernet_0** block. Change //Physical Interface Selection// to **RGMII** and click OK.
-  * Route **clk_out2** on your //Clocking Wizard// block to **sys_clk_i** on the //Memory Interface Generator// block. +
-  * Route **clk_out3** on your //Clocking Wizard// block to **clk_ref_i** on the //Memory Interface Generator// block.+
  
-{{:arty:4.jpg?nolink|}}+{{:nexys:nexysvideo:9.jpg?nolink|}}
  
-13. Click //"Run Connection Automation"//. Un-check the //microblaze_0// check-box and click OK.+Click //"Run Connection Automation"//. Un-check the **microblaze_0** check-box and click OK.
  
-{{:arty:6.jpg?nolink|}}+{{:nexys:nexysvideo:10.jpg?nolink|}}
  
-14. Click //Regenerate Layout// (circled in blue below), and your block design should look like this:+14. Click //"Run Connection Automation"// again. Run this for the **axi_ethernet_0_dma**.
  
-{{:arty:7.jpg?nolink|8-)}}+{{:nexys:nexysvideo:11.jpg?nolink|}}
  
-15.  +15. Click //Regenerate Layout// (circled in blue below), and your block design should look like this:
-  * Route **interrupt** on the //AXI Timer// block to **In0[0:0]** on the //Concat// block. +
-  * Route **ip2intc_irpt** on the //AXI EthernetLite// block to **In1[0:0]** on the //Concat// block.+
  
-{{:nexys4-ddr:server_13.jpg?nolink|}}+{{:nexys:nexysvideo:12.jpg?nolink|}}
  
-  * Connect **resetn** on the //Clocking Wizard// block to the **reset** pin.+==== Routing the Missing Connections ====
  
-{{:nexys4-ddr:server_14.jpg?nolink|}}+16. The //Concat// block takes interrupt inputs and sends them to the Microblaze controller. 
 +  
 +{{:nexys:nexysvideo:concat.jpg?nolink&200|}}
  
-16. Right click somewhere in the background (white space) of your design and click //Create Port...//, or use the shortcut, Ctrl-K. Name this port eth_ref_clk and change the options to the one in the picture below.+**Route the following connections to the inputs of the //Concat// block.** Order does not matter. 
 +  * **interrupt** on the //AXI Timer// block. 
 +  * **mm2s_introut** and **s2mm_introut** on the //axi_ethernet_0_dma// block. 
 +  * **mac_irq** and **interrupt** on the //axi_ethernet_0// block.
  
-{{:nexys4-ddr:server_15.jpg?nolink|}}+{{:nexys:nexysvideo:13.jpg?nolink|}}
  
-17. Connect this **eth_ref_clk** pin to **clk_out4** on the //Clocking Wizard// block.+17. 
 +  * Connect **resetn** on the //Clocking Wizard// block to the **reset** pin input.
  
-{{:arty:8.jpg?nolink|}}+{{:nexys4-ddr:server_14.jpg?nolink|}}
  
-18. Right click on the blue striped rectangle next to the **DDR3+** bus on the //Memory Interface Generator// block and click //"Make External"//.+18. 
 +  * Connect **sys_clk_i** on the //mig_7_series_0// block to the **clk_out2** output from the //Clocking Wizard//.
  
-{{:arty:9.jpg?nolink|}}+{{:nexys:nexysvideo:14.jpg?nolink|}}
  
-19. Clicking //Regenerate Layout// again will result in your final block design layout for this project.+19. Right click on the blue striped rectangle next to the **DDR3+** bus on the //Memory Interface Generator// block and click //"Make External"//.
  
-{{:arty:10.jpg?nolink|}} +{{:arty:9.jpg?nolink|}}
- +
-20. We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under the //Design// window, select the **Sources** tab. Expand the //contraints// folder, right click on //constr// and click "Add Sources..." +
- +
-{{:nexys4-ddr:server_19.jpg?nolink|}} +
- +
-21. Select Add or create constraints and click Next. +
- +
-{{:nexys4-ddr:server_20.jpg?nolink|}} +
- +
-22. Click //Create File...//, name your new contraints file and click OK and then Finish.+
  
-{{:nexys4-ddr:server_21.jpg?nolink|}}+20. Clicking //Regenerate Layout// again will result in your final block design layout for this project.
  
-23. Open your new constraints file and paste the following line of code in it:+{{:nexys:nexysvideo:15.jpg?nolink|}}
  
-  set_property -dict { PACKAGE_PIN G18    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk +21. Click the **Validate Design** {{:nexys:nexysvideo:validate.jpg?nolink|}} button to make sure that you did not make any errors.
-   +
-Save the xdc file when you are finished.+
  
-24. Now, right click on your design_1 block diagram and click //"Create HDL Wrapper"//. When the window pops up, select the "Let Vivado manage wrapper and auto-update" bullet and click OK.+22. Now, right click on your design_1 block diagram and click //"Create HDL Wrapper"//. When the window pops up, select the "Let Vivado manage wrapper and auto-update" bullet and click OK.
  
 {{:nexys4-ddr:server_22.jpg?nolink|}} {{:nexys4-ddr:server_22.jpg?nolink|}}
  
-25. Click "Generate Bitstream" at the top of the work space. This process will take a while.+23. Click "Generate Bitstream" at the top of the work space. This process will take a while.
  
 {{:nexys4-ddr:server_23.jpg?nolink|}} {{:nexys4-ddr:server_23.jpg?nolink|}}
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 ==== Exporting Hardware Design to SDK ==== ==== Exporting Hardware Design to SDK ====
  
-26. On the top left corner of the window, from the tool bar click on //File// and select //Export Hardware//.+24. On the top left corner of the window, from the tool bar click on //File// and select //Export Hardware//.
 This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.  This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. 
 **Make sure the generated bitstream is included by checking the box**. **Make sure the generated bitstream is included by checking the box**.
- 
-**There is currently a bug where the //download.bit// file is not generated for the Nexys Video board. To work around this, click File>Export>Export Bitstream File... then navigate to project/project.sdk/design_1_wrapper_hw_platform_0 and export a new bit file called "download"** 
  
 {{:nexys4-ddr:server_24.jpg?nolink|}} {{:nexys4-ddr:server_24.jpg?nolink|}}
- 
- 
  
 ==== Launching SDK ==== ==== Launching SDK ====
  
-27. Go to //File// and select //Launch SDK// and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete. +25. Go to //File// and select //Launch SDK// and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete. 
  
 {{:vivado:mig_45.jpg|}} {{:vivado:mig_45.jpg|}}
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 ==== Inside SDK for Vivado ==== ==== Inside SDK for Vivado ====
  
-28. A new window for SDK will open. The HW design specification and included IP blocks are displayed in the //system.hdf// file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory. +26. A new window for SDK will open. The HW design specification and included IP blocks are displayed in the //system.hdf// file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory. 
  
 Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.  Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK. 
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 ==== Creating New Application Project in SDK ==== ==== Creating New Application Project in SDK ====
  
-29. Go to //File// in the main tool bar and select **New >> Application Project**. A new project window will pop up. +27. Go to //File// in the main tool bar and select **New >> Application Project**. A new project window will pop up. 
 Give your SDK project a name that has no empty spaces as shown below. Make sure the //Target Hardware// is the correct hardware design. In our case, it will be "design_1_wrapper_hw_platform_0".  Give your SDK project a name that has no empty spaces as shown below. Make sure the //Target Hardware// is the correct hardware design. In our case, it will be "design_1_wrapper_hw_platform_0". 
  
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 {{:nexys4-ddr:server_26.jpg?nolink|}} {{:nexys4-ddr:server_26.jpg?nolink|}}
  
-30. After completing the previous step, you will see two new folders in the //Project Explorer// panel. +28. After completing the previous step, you will see two new folders in the //Project Explorer// panel. 
   * **echo_server** which contains all the binaries, .C and .H (Header) files   * **echo_server** which contains all the binaries, .C and .H (Header) files
   * **echo_server_bsp** which is the board support folder    * **echo_server_bsp** which is the board support folder 
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 ==== Verify Linker Script File for Memory Region Mapping ==== ==== Verify Linker Script File for Memory Region Mapping ====
  
-31. In the linker script, take a look at the **Section to Memory Region Mapping** box. If you did the //Make DDR2 External// step then the target memory region **must** read **mig_7series_0**. +29. In the linker script, take a look at the **Section to Memory Region Mapping** box. If you did the //Make DDR2 External// step then the target memory region **must** read **mig_7series_0**. 
  
 Scroll down to check if this applies to all rows.  If for any region it does not say **mig_7series_0**, then click on the row under the **Memory Region** column and select **mig_7series_0**. Scroll down to check if this applies to all rows.  If for any region it does not say **mig_7series_0**, then click on the row under the **Memory Region** column and select **mig_7series_0**.
  
 {{:nexys4-ddr:server_28.jpg?nolink|}} {{:nexys4-ddr:server_28.jpg?nolink|}}
 +
 +==== Setting PHY Link Speed ====
 +
 +30. Open the //system.mss// file within the //echo_server_bsp// folder and click **Modify this BSP's Settings**.
 +
 +{{:nexys4-ddr:server_30.jpg?nolink|}}
 +
 +Select //lwip140//, then expand the //temac_adapter_options// and find //phy_link_speed// in the list. Change the value of //phy_link_speed// to **CONFIG_LINKSPEED1000** and press OK.
 +
 +{{:nexys4-ddr:server_31.jpg?nolink|}}
  
 ==== Programming FPGA with Bit File ==== ==== Programming FPGA with Bit File ====
  
-32. Make sure that the Nexys Video is turned on and connected to the host PC with the provided micro USB cable. +31. Make sure that the Nexys Video is turned on and connected to the host PC with the provided micro USB cable plugged into the Prog port on the Nexys Video. 
  
 On the main toolbar, click **Xilinx Tools>>Program FPGA**  On the main toolbar, click **Xilinx Tools>>Program FPGA** 
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 ==== Setting up the SDK Serial Console and Running the Server ==== ==== Setting up the SDK Serial Console and Running the Server ====
  
-33. Right click on the //echo_server// project folder and select **Run As >> Run Configurations**+32. Right click on the //echo_server// project folder and select **Run As >> Run Configurations**
  
 {{:nexys4-ddr:server_32.jpg?nolink|}} {{:nexys4-ddr:server_32.jpg?nolink|}}
  
-Go to the //STDIO Connection// tab and check the //Connect STDIO to Console// check-box. Click //Apply//, then click //Run//.+**Move the USB plug from the Prog port on your board to the UART port**. Now go to the //STDIO Connection// tab and check the //Connect STDIO to Console// check-box. Click //Apply//, then click //Run//.
  
 {{:nexys4-ddr:server_33.jpg?nolink|}} {{:nexys4-ddr:server_33.jpg?nolink|}}
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 ==== Running the Server ==== ==== Running the Server ====
  
-34. In the console window at the bottom of the screen the details of the connection will be displayed.+33. In the console window at the bottom of the screen the details of the connection will be displayed.
  
 {{:nexys4-ddr:server_34.jpg?nolink|}} {{:nexys4-ddr:server_34.jpg?nolink|}}
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 ==== Testing the Server with Tera Term ==== ==== Testing the Server with Tera Term ====
  
-35. Connect your PC to your Nexys Video using an Ethernet cable.+34. Connect your PC to your Nexys Video using an Ethernet cable.
  
-36. In order to connect to the echo server, you must set up your Ethernet connection with a static IP address. To do this:+35. In order to connect to the echo server, you must set up your Ethernet connection with a static IP address. To do this:
   * Right click your internet connection and click //Open Network and Sharing Center//.   * Right click your internet connection and click //Open Network and Sharing Center//.
  
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 {{:nexys4-ddr:server_39.jpg?nolink|}} {{:nexys4-ddr:server_39.jpg?nolink|}}
  
-38. Open Tera Term and type in the following info and click Ok.+36. Open Tera Term and type in the following info and click Ok.
 {{:nexys4-ddr:server_40.jpg?nolink|}} {{:nexys4-ddr:server_40.jpg?nolink|}}
  
-39. Type anything into the console and press Enter. The echo server will echo back your input and display it in the console.+37. Type anything into the console and press Enter. The echo server will echo back your input and display it in the console.
  
 //You can go to Setup>Terminal and change the settings below for a more traditional echo server format// //You can go to Setup>Terminal and change the settings below for a more traditional echo server format//
  
 {{:nexys4-ddr:11.jpg?nolink|}} {{:nexys4-ddr:11.jpg?nolink|}}