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| nexys:nexys4_ddr:start [2014/12/10 19:37] – [Introduction Draft] Varun Kondagunturi | nexys:nexys4_ddr:start [2015/01/15 00:32] (current) – removed sbobrowicz | ||
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| - | ====== Nexys 4 DDR ====== | ||
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| - | **Insert Official Image Here** | ||
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| - | ----- | ||
| - | ===== Introduction Draft ===== | ||
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| - | The Nexys 4 DDR is the latest addition to the Nexys line of Digilent FPGA board designed exclusively for the Vivado Design Suite, featuring Xilinx XC7A100T Artix 7-FPGA architecture. Nexys 4 DDR as the name suggests, packs a DDR2 external memory. Has additional slide switches, leds compared to Nexys 4.... | ||
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| - | For more information, | ||
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| - | **Insert Youtube link for SamB's N4DDR' | ||
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| - | ---- | ||
| - | ===== Documentation ===== | ||
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| - | * **Schematic** -- [[**Insert Schematic PDF Here**]] | ||
| - | * PDF Schematic of the PCB generated by Altium | ||
| - | * **Reference Manual** -- [[refmanual|Wiki]] [[**Insert REFMAN PDF Here**]] | ||
| - | * Technical description of the Nexys4 DDR and all of its features. The Wiki may contain more up-to-date information than the PDF. | ||
| - | * **Getting Started Guide** -- [[gsg|Wiki]] | ||
| - | * Great starting point for new Nexys4 DDR owners. Includes the kit contents, instructions for running the out of box demo, and instructions for building a simple design. | ||
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| - | ===== Design Resources ===== | ||
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| - | * **Master XDC** -- [[**Insert Master XDC Link Here**]] | ||
| - | * This package contains the master XDC that defines the pin constraints for every device on the Nexys4 DDR. | ||
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| - | * **Master UCF** -- [[**Insert Master UCF Link Here**]] | ||
| - | * This package contains the master UCF that defines the pin constraints for every device on the Nexys4 DDR. | ||
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| - | ===== Reference Projects ===== | ||
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| - | * **General I/O Demo** -- [[gpiodemo|Wiki]] | ||
| - | * Basic demo that uses the onboard switches, buttons, leds, 7-segment display, UART, a VGA monitor and a USB-HID mouse. This project is pre-loaded into SPI flash when the board is shipped. | ||
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| - | ====== Getting Started with Vivado IP Integrator ====== | ||
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| - | * **Getting Started with Vivado IP Integrator** - [[Nexys4 DDR: | ||
| - | * Follow this simple introduction on using the Vivado IP Integrator. | ||
| - | * IP blocks for Microblaze, Memory Interface Generator (MIG) and UART will be added to run a Hello World bare-metal project on the Nexys 4 DDR. | ||
| - | * 2014.3 Vivado and SDK will be used. | ||
| - | * Before running the Vivado IP Integrator demo, please refer to the Wiki page: [[vivado: | ||
| - | * Please refer to this Wiki page [[vivado: | ||
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| - | ---- | ||
| - | ===== FAQ ===== | ||
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| - | This list will be populated as common questions are identified on the [[http:// | ||
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| - | Currently no entries. | ||
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| - | ---- | ||
| - | ===== External Links ===== | ||
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| - | * [[http:// | ||
| - | * [[http:// | ||
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