Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
nexys:nexys4:refmanual [2014/09/11 00:16] – [9 Basic I/O] Joshua Woldstadnexys:nexys4:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 45: Line 45:
 | **1**        | Power select jumper and battery header    | **13**       | FPGA configuration reset button       | | **1**        | Power select jumper and battery header    | **13**       | FPGA configuration reset button       |
 | **2**        | Shared UART/ JTAG USB port                | **14**       | CPU reset button (for soft cores)     | | **2**        | Shared UART/ JTAG USB port                | **14**       | CPU reset button (for soft cores)     |
-| **3**        | External configuration jumper (SD / USB)  | **15**       | Analog signal Pmod connector (XADC)   | +| **3**        | External configuration jumper (SD / USB)  | **15**       | Analog signal Pmod port (XADC)   | 
-| **4**        | Pmod connector(s)                         | **16**       | Programming mode jumper               |+| **4**        | Pmod port(s)                         | **16**       | Programming mode jumper               |
 | **5**        | Microphone                                | **17**       | Audio connector                       | | **5**        | Microphone                                | **17**       | Audio connector                       |
 | **6**        | Power supply test point(s)                | **18**       | VGA connector                         | | **6**        | Power supply test point(s)                | **18**       | VGA connector                         |
Line 149: Line 149:
 The 16Mbyte Cellular RAM (Micron part number M45W8MW16) has a 16-bit bus that supports 8 or 16 bit data access. It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns, or as a synchronous memory with a 104MHz bus. When operated as an asynchronous SRAM, the Cellular RAM automatically refreshes its internal DRAM arrays, allowing for a simplified memory controller (similar to any SRAM controller). When operated in synchronous mode, continuous transfers of up to 104MHz are possible.  The 16Mbyte Cellular RAM (Micron part number M45W8MW16) has a 16-bit bus that supports 8 or 16 bit data access. It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns, or as a synchronous memory with a 104MHz bus. When operated as an asynchronous SRAM, the Cellular RAM automatically refreshes its internal DRAM arrays, allowing for a simplified memory controller (similar to any SRAM controller). When operated in synchronous mode, continuous transfers of up to 104MHz are possible. 
  
-FPGA configuration files can be written to the Quad SPI Flash (Spansion part number S25FL128S), and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data. +FPGA configuration files can be written to the Quad SPI Flash (Spansion part number S25FL128), and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data. 
  
 **NOTE: Refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website for more information about the memory devices. **NOTE: Refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website for more information about the memory devices.
Line 379: Line 379:
 Note: Digilent strongly recommends the use of Pulse-Width Modulation (PWM) when driving the tri-color LEDs (for information on PWM, see section 15.1). Driving any of the inputs to a steady logic ‘1’ will result in the LED being illuminated at an uncomfortably bright level. You can avoid this by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color led. Individually adjusting the duty cycle of each color between 50% and 0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed. Note: Digilent strongly recommends the use of Pulse-Width Modulation (PWM) when driving the tri-color LEDs (for information on PWM, see section 15.1). Driving any of the inputs to a steady logic ‘1’ will result in the LED being illuminated at an uncomfortably bright level. You can avoid this by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color led. Individually adjusting the duty cycle of each color between 50% and 0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed.
  
-====== 10 PMOD Connectors ======+====== 10 PMOD Ports ======
  
-The Pmod connectors are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6 pin headers.. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig 20. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. Pin assignments for the Pmod I/O connected to the FPGA are shown in Table 6.+The Pmod ports are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6 pin headers.. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig 20. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. Pin assignments for the Pmod I/O connected to the FPGA are shown in Table 6.
 {{ :nexys:nexys4:pmod1.png?300 |}} {{ :nexys:nexys4:pmod1.png?300 |}}
  
 +//Figure 20. PMOD Ports- Front view as loaded on PCB
 +//
 +
 +| **Pmod JA**  | **Pmod JB**  | **Pmod JC**  | **Pmod JD**  | **Pmod XDAC**  |
 +| JA1: B13     | JP1: G14     | JC1: K2      | JD1: H4      | JXADC1: A13    |
 +| JA2: F14     | JB2: P15     | JC2: E7      | JD2: H1      | JXADC2: A15    |
 +| JA3: D17     | JB3: V11     | JC3: J3      | JD3: G1      | JXADC3: B16    |
 +| JA4: E17     | JB4: V15     | JC4: J4      | JD4: G3      | JXADC4: B18    |
 +| JA7: G13     | JB7: K16     | JC7: K1      | JD7: H2      | JXADC7: A14    |
 +| JA8: C17     | JB8: R16     | JC8: E6      | JD8: G4      | JXADC8: A16    |
 +| JA9: D18     | JB9: T9      | JC9: J2      | JD9: G2      | JXADC9: B17    |
 +| JA10: E18    | JB10: U11    | JC10: G6     | JD10: F3     | JXADC10: A18   |
 +
 +//Table 6. Nexys4 Pmod Pin Assignments
 +//
 +
 +Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information.
 +
 +==== 10.1 Dual Analog/ Digital Pmod ====
 +
 +The on-board Pmod expansion connector labeled “JXADC” is wired to the auxiliary analog input pins of the FPGA. Depending on the configuration, this connector can be used to input differential analog signals to the analog-to-digital converter inside the Artix-7 (XADC). Any or all pairs in the connector can be configured either as analog input or digital input-output. 
 +
 +The Dual Analog/Digigal Pmod on the Nexys4differs from the rest in the routing of its traces. The eight data signals are grouped into four pairs, with the pairs routed closely coupled for better analog noise immunity. Furthermore, each pair has a partially loaded anti-alias filter laid out on the PCB. The filter does not have capacitors C60-C63. In designs where such filters are desired, the capacitors can be manually loaded by the user.
 +
 +NOTE: The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals.
 +
 +The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.”
 +
 +----
 +
 +====== 11 MicroSD Slot ======
 +
 +The Nexys4 provides a microSD slot for both FPGA configuration and user access. The on-board Auxiliary Function microcontroller shares the SD card bus with the FPGA. Before the FPGA is configured the microcontroller must have access to the SD card via a SPI interface. Once a bit file is downloaded to the FPGA (from any source), the microcontroller power cycles the SD slot and relinquishes control of the bus. This enables any SD card in the slot to reset its internal state machines and boot up in SD native bus mode. All of the SD pins on the FPGA are wired to support full SD speeds in native interface mode, as shown in Fig 21. The SPI interface is also available, if needed. Once control over the SD bus is passed from the microcontroller to the FPGA, the SD_RESET signal needs to be actively driven low by the FPGA to power the microSD card slot.  For information on implementing an SD card controller, refer to the SD card specification available at www.sdcard.org. 
 +
 +{{ :nexys:nexys4:micro1.png?300 |}}
 +
 +//Figure 21. Artix-7 microSD card connector interface (PIC24 connections not shown)
 +//
 +
 +----
 +
 +====== 12 Temperature Sensor ====== 
 +
 +The Nexys4 includes an Analog Device ADT7420 temperature sensor. The sensor provides up to 16-bit resolution with a typical accuracy better than 0.25 degrees Celsius. The interface between the temperature sensor and FPGA is shown in Fig 22.
 +
 +{{ :nexys:nexys4:temp1.png?600 |}}
 +
 +==== 12.1 I2C Interface ====
 +
 +The ADT7420 chip acts as a slave device using the industry standard I2C communication scheme. To communicate with ADT7420 chip, the I2C master must specify a slave address (0x4B) and a flag indicating whether the communication is a read (1) or a write (0). Once specifications are made for communication, a data transfer takes place. For ADT7420, the data transfer should consist of the address of the desired device register followed by the data to be written to the specified register. To read from a register, the master must write the desired register address to the ADT7420, then send an I2C restart condition, and send a new read request to the ADT7420. If the master does not generate a restart condition prior to attempting the read, the value written to the address register will be reset to 0x00.
 +
 +As some registers store 16-bit values as 8-bit register pairs, the ADT7420 will automatically increment the address register of the device when accessing certain registers, such as the temperature registers and the threshold registers. This allows for the master to use a single read or write request to access both the low and high bytes of these registers. A complete listing of registers and their behavior can be found in the ADT7420 datasheet available on the Analog Devices web site.
 +
 +==== 12.2 Open Drain Outputs ====
 +
 +The ADT7420 provides two open drain output signals to indicate when pre-set temperature thresholds are reached. If the temperature leaves a range defined by registers TLOW (0x06:0x07) and THIGH (0x04:0x05), the INT pin can be driven low or high based upon the configuration of the device. Similarly, the CT pin can be driven low or high if the temperature exceeds a critical threshold defined in TCRIT (0x08:0x09). Both of these pins need internal FPGA pull-ups when used. 
 +
 +For details on the electrical specifications and configuration of the INT and CT pins, refer to the ADT7420 datasheet.
 +
 +==== 12.3 Quick Start Operation ====
 +
 +When the ADT7420 is powered up, it is in a mode that can be used as a simple temperature sensor without any initial configuration. By default, the device address register points to the temperature MSB register, so a two byte read without specifying a register will read the value of the temperature register from the device. The first byte read back will be the most significant byte (MSB) of the temperature data, and the second will be the least significant byte (LSB) of the data. These two bytes form a two’s complement 16-bit integer. If the result is shifted to the right three bits and multiplied by 0.0625, the resulting signed floating point value will be a temperature reading in degrees Celsius.
 +
 +For information on reading and writing to the other registers of the device, as well as notes on the accuracy of the temperature measurements, refer to the ADT7420 datasheet.
 +
 +----
 +
 +====== 13 Accelerometer ======
 +
 +The Nexys4 includes an Analog Device ADXL362 accelerometer. The ADXL362 is a 3-axis MEMS accelerometer that consumes less than 2 μA at a 100 Hz output data rate and 270 nA when in motion triggered wake-up mode. Unlike accelerometers that use power duty cycling to achieve low power consumption, the ADXL362 does not alias input signals by under-sampling; it samples the full bandwidth of the sensor at all data rates. The ADXL362 always provides 12-bit output resolution; 8-bit formatted data is also provided for more efficient single-byte transfers when a lower resolution is sufficient. Measurement ranges of ±2 g, ±4 g, and ±8 g are available, with a resolution of 1 mg/LSB on the ±2 g range. The FPGA can talk with the ADXL362 via SPI interface. While the ADXL362 is in Measurement Mode, it continuously measures and stores acceleration data in the X-data, Y-data, and Z-data registers. The interface between the FPGA and accelerometer can be seen in Fig 23.
 +
 +{{ :nexys:nexys4:acc1.png?450 |}}
 +
 +//Figure 23. Accelerometer interface//
 +
 +
 +==== 13.1 SPI Interface ====
 +
 +The ADXL362 acts as a slave device using an SPI communication scheme. The recommended SPI clock frequency ranges from 1MHz to 5MHz. The SPI interface operates in SPI mode 0 with CPOL = 0 and CPHA = 0. All communications with the device must specify a register address and a flag that indicate whether the communication is a read or a write. Actual data transfer always follows the register address and communication flag. Device configuration can be performed by writing to the control registers within the accelerometer. Access accelerometer data by reading the device registers. 
 +
 +For a full list of registers, their functionality, and communication specifications, see the ADXL362 datasheet available at: www.analog.com.
 +
 +==== 13.2 Interrupts ====
 +
 +Several of the built-in functions of the ADXL362 can trigger interrupts that alert the host processor of certain status conditions. Interrupts can be mapped to either (or both) of two interrupt pins (INT1, INT2). Both of these pins require internal FPGA pull-ups when used. For more details about the interrupts, see the ADXL362 datasheet available at: www.analog.com.
 +
 +----
 +
 +====== 14 Microphone ======
 +
 +The Nexys4 board includes an omnidirectional MEMS microphone. The microphone uses an Analog Device ADMP421 chip which has a high signal to noise ratio (SNR) of 61dBA and high sensitivity of -26 dBFS. It also has a flat frequency response ranging from 100Hz to 15kHz. The digitized audio is output in the pulse density modulated (PDM) format.
 +
 +The component architecture is shown in Figure 24.
 +
 +{{ :nexys:nexys4:mic1.png?600 |}}
 +
 +//Figure 24. Microphone Block Diagaram
 +//
 +
 +==== 14.1 Pulse Density Modulation (PDM) ====
 +
 +PDM data connections are becoming more and more popular in portable audio applications, such as cellphones and tablets. With PDM, two channels can be transmitted with only two wires. The frequency of a PDM signal usually falls in the range of 1MHz to 3MHz. In a PDM bit stream, a 1 corresponds a positive pulse and a 0 corresponds a negative pulse. A run consisting of all ‘1’s would corresponds to the maximum positive value and a run of ‘0’s would corresponds to the minimum amplitude value. Figure 25 shows how a sine wave is represented in PDM signal.
 +
 +{{ :nexys:nexys4:mic2.png?500 |}}
 +
 +//Figure 25. PDM representation of a sine wave//
 +
 +A PDM signal is generated from an analog signal through a process called Delta-Sigma Modulation. A simple idealized circuit of Delta-Sigma Modulator is shown as Figure 26.
 +
 +{{ :nexys:nexys4:mic3.png?300 |}}
 +
 +//Figure 26. Simple Delta-Sigma Modulator Circuit//
 +
 +^ Sum     ^ Integrator Out  ^ Flip-flop Output  ^
 +| 0.4-0=0.4   | 0+0.4=0.4       | 0                 |
 +| 0.4-0=0.4   | 0.4+0.4=0.8     | 1                 |
 +| 0.4-1=-0.6  | 0.8-0.6=0.2     | 0                 |
 +| 0.4-0=0.4   | 0.2+0.4=0.6     | 1                 |
 +| 0.4-1=-0.6  | 0.6-0.6=0       | 0                 |
 +| 0.4-0=0.4   | 0+0.4=0.4       | 0                 |
 +| 0.4-0=0.4   | 0.4+0.4=0.8     | 1                 |
 +| 0.4-1=-0.6  | 0.8-0.6=0.2     | 0                 |
 +
 +//Table 7. Sigma Delta Modulator with a 0.4Vdd input//
 +
 +To keep things simple here, assume that the analog input and digital output have the same voltage range 0~Vdd. The input of the flip-flop acts like a comparator (any signal above Vdd/2 is considered as ‘1’ and any input bellow Vdd/2 is considered ‘0’). The input of the integral circuit is the difference of the input analog signal and the PDM signal of the previous clock cycle. Then the integral circuit integrates both these inputs, and the output of the integral circuit is sampled by a D-Flip-flop. Table 7 shows the function of the delta-sigma modulator with an input of 0.4Vdd.
 +
 +Note that the average of the flip-flop output equals the value of the input analog signal. So, in order to get the value of analog input, all that is needed is a counter that counts the ‘1’s for a certain period of time
 +
 +==== 14.2 Microphone Digital Interface Timing ====
 +
 +The clock input of the microphone can range from 1MHz to 3.3MHz based on the sampling rate and data precision requirement of the applications. The L/R Select signal must be set to a valid level, depending on which edge of the clock the data bit will be read. A low level on L/RSEL makes data available on the rising edge of the clock, while a high level corresponds to the falling edge of the clock, as shown in Fig 27.
 +
 +{{ :nexys:nexys4:mic4.png?500 |}}
 +//Figure 27. PDM Timing Diagram//
 +
 +The typical value of the clock frequency is 2.4MHz. Assuming that the application requires 7-bit precision and 24KHz, there can be two counters that count 128 samples at 12KHz, as shown in Fig 28.
 +{{ :nexys:nexys4:mic5.png?400 |}}
 +
 +//Figure 28. Sampling PDM with two counters//
 +
 +----
 +
 +====== 15 Mono Audio Output ======
 +
 +The on-board audio jack (J8) is driven by a Sallen-Key Butterworth Low-pass 4th Order Filter that provides mono audio output. The circuit of the low pass filter is shown in Fig 29. The input of the filter (AUD_PWM) is connected to the FPGA pin A11. A digital input will typically be a pulse width modulated (PWM) signal or pulse density modulated (PDM) signal produced by the FPGA. The low pass filter on the input will act as a reconstruction filter to convert the pulse width modulated digital signal into an analog voltage on the audio jack output.
 +
 +{{ :nexys:nexys4:mono1.png?700 |}}
 +//Figure 29. Sallen-Key Butterworth Low Pass 4th Order Fliter//
 +
 +The frequency response of SK Butterworth Low Pass Filter is shown in Fig 30. The AC analysis of the circuit is done using NI Multism 12.0.
 +
 +{{ :nexys:nexys4:mono2.png?500 |}}
 +
 +//Figure 30. SK Butterworth Low Pass Filter frequency response//
 +
 +==== 15.1 Pulse-Width Modulation ====
 +
 +A pulse-width modulated (PWM) signal is a chain of pulses at some fixed frequency, with each pulse potentially having a different width. This digital signal can be passed through a simple low-pass filter that integrates the digital waveform to produce an analog voltage proportional to the average pulse width over some interval (the interval is determined by the 3dB cut-off frequency of the low pass filter and the pulse frequency). For example, if the pulses are high for an average of 10% of the available pulse period, then an integrator will produce an analog value that is 10% of the Vdd voltage. Figure 31 shows a waveform represented as a PWM signal.
 +
 +{{ :nexys:nexys4:mono3.png?600 |}}
 +
 +//Figure 31. Simple Waveform represented as PWM//
 +
 +The PWM signal must be integrated to define an analog voltage. The low pass filter 3dB frequency should be an order of magnitude lower than the PWM frequency, so that signal energy at the PWM frequency is filtered from the signal. For example, if an audio signal must contain up to 5KHz of frequency information, then the PWM frequency should be at least 50KHz (and preferably even higher). In general, in terms of analog signal fidelity, the higher the PWM frequency, the better. Figure 32 shows a representation of a PWM integrator producing an output voltage by integrating the pulse train. Note the steady-state filter output signal amplitude ratio to Vdd is the same as the pulse width duty cycle (duty cycle is defined as pulse-high time divided by pulse-window time).
 +
 +{{ :nexys:nexys4:mono4.png?300 |}}
 +//Figure 32. Representation of a PWM integrator producing an output voltage by integrating the pulse train//
 +
 +----
 +
 +====== 16 Built-In Self-Test ======
 +
 +A demonstration configuration is loaded into the SPI Flash device on the Nexys4 board during manufacturing. The source code and prebuilt bitstream for this design are available for download from the Digilent website. If the demo configuration is present in the SPI Flash device and the Nexys4 board is powered on in SPI mode, the demo project will allow basic hardware verification. Here is an overview of how this demo drives the different onboard components:
 +
 +  * The user LEDs are illuminated when the corresponding user switch is placed in the on position.
 +  * The tri-color LEDs are controlled by some of the user buttons. Pressing BTNL, BTNC, or BTNR causes them to illuminate either red, green or blue, respectively. Pressing BTND causes them to begin cycling through many colors. Repeatedly pressing BTND will turn the two LEDs on or off.
 +  * Pressing BTNU will trigger a 5 second recording from the onboard PDM microphone. This recording is then immediately played back on the mono audio out port. The status of the recording and playback is displayed on the user LEDs.
 +  * The VGA port displays feedback from the onboard microphone, temperature sensors, accelerometer, RGB LEDs, and USB Mouse.
 +  * Connecting a mouse to the USB-HID Mouse port will allow the pointer on the VGA display to be controlled. Note that some Microsoft mice have difficulty communicating with this demo.
 +  * On power-up, the seven-segment display will show the results of an automated test for the onboard CellRAM, accelerometer, and temperature sensor. It will then display a moving snake pattern. Note that the accelerometer test will fail if the board is on an unstable or un-level surface when it is powered on, and the temperature sensor test may fail if the board is in an extreme thermal climate. With these two considerations in mind, if your board is reporting a failure, make note of the error code and create a post on our [[https://forum.digilent.com|forum]]. 
 +
 +All Nexys4 boards are 100% tested during the manufacturing process. If any device on the Nexys4 board fails test or is not responding properly, it is likely that damage occurred during transport or during use. Typical damage includes stressed solder joints and contaminants in switches and buttons resulting in intermittent failures. Stressed solder joints can be repaired by reheating and reflowing solder and contaminants can be cleaned with off-the-shelf electronics cleaning products. If a board fails test within the warranty period, it will be replaced at no cost. Contact Digilent for more details.