Differences
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| Next revision | Previous revision | ||
| netfpga-1g-cml:refmanual [2015/09/08 20:21] – created Martha | netfpga-1g-cml:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| Line 18: | Line 18: | ||
| * Crypto-authentication chip | * Crypto-authentication chip | ||
| * High pin count FMC connector (VITA 57) withh 100 Select-IO and 4 GTX serial pairs | * High pin count FMC connector (VITA 57) withh 100 Select-IO and 4 GTX serial pairs | ||
| - | * Two Pmod connectors | + | * Two Pmod ports |
| * Four on-board LEDs and four on-board general-purpose buttons | * Four on-board LEDs and four on-board general-purpose buttons | ||
| Line 199: | Line 199: | ||
| ---- | ---- | ||
| - | ====== Pmod Expansion | + | ====== Pmod Expansion |
| - | The NetFPGA-1G has two 12-pin | + | The NetFPGA-1G has two 12-pin |
| - | {{ : | + | {{ : |
| ---- | ---- | ||
| Line 248: | Line 248: | ||
| - Plug the NetFPGA-7 into the HTG PCIe test card. Loop the RX0-3 pairs on the HTG card to the TX0-4 pairs using SMA cables (RX0P <-> TX0P, RX0N <-> TX0N, etc.). Set switches 1-3 on the HTG card to 000. Additionally, | - Plug the NetFPGA-7 into the HTG PCIe test card. Loop the RX0-3 pairs on the HTG card to the TX0-4 pairs using SMA cables (RX0P <-> TX0P, RX0N <-> TX0N, etc.). Set switches 1-3 on the HTG card to 000. Additionally, | ||
| - Plug a PCIe power connector from a standard PC power supply into J17 on the NetFPGA-7 | - Plug a PCIe power connector from a standard PC power supply into J17 on the NetFPGA-7 | ||
| - | - If FPGA debug information is desired, connect the additional PmodUSBUART, | + | - If FPGA debug information is desired, connect the additional PmodUSBUART, |
| Many tests can be run independently without the need for additional hardware. For example, the HiTech Global Breakout Board is only needed to test the PCIe edge connector. More details regarding individual tests are provided in the // | Many tests can be run independently without the need for additional hardware. For example, the HiTech Global Breakout Board is only needed to test the PCIe edge connector. More details regarding individual tests are provided in the // | ||
| Line 567: | Line 567: | ||
| | NET btn_3 | LOC = AB6 | IOSTANDARD = LVCMOS15; | | NET btn_3 | LOC = AB6 | IOSTANDARD = LVCMOS15; | ||
| - | ===== Pmod Connectors | + | ===== Pmod Ports ===== |
| ^ Port Name ^ IO Location | ^ Port Name ^ IO Location | ||

