This is an old revision of the document!
This is the landing page for all of the Verilog based projects that will be dynamically loaded into a nice list, but I haven't bothered doing so just yet. Also need to consider how to make sure that we don't get all of the projects on the main Vivado page (and just this landing page) so we don't clutter it unnecessarily.
For now, you can view the list of projects listed statically below:
- A pseudo Project 0 for those wanting to learn how to navigate Vivado in general.
- Project 1 for learning the major keywords and concepts.
- Project 2 for programming an FPGA for the first time.
A list of some other potentially useful resources is available below:
- Some history and background on Verilog
- What is an XDC file and how does it interface with my Vivado code