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learn:software:tutorials:verilog-project-2:start [2021/10/13 22:31] – Arthur Brownlearn:software:tutorials:verilog-project-2:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ===== Some Background Information =====  ===== Some Background Information ===== 
-The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[learn/software/tutorials/vivado-xdc-file|XDC file]]) +The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[programmable-logic:guides:vivado-xdc-file|XDC file]]) 
  
 ===== Relooking at the Simple Example HDL =====  ===== Relooking at the Simple Example HDL ===== 
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 >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}}
  
-> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[learn/software/tutorials/vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty]], I used the Master XDC available on it's [[programmable-logic:arty:start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.+> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[programmable-logic:guides:vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty]], I used the Master XDC available on it's [[programmable-logic:arty:start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.
 > >
 >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}}
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 >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}}
  
-> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[learn/software/tutorials/vivado-xdc-file|XDC file here]].+> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[programmable-logic:guides:vivado-xdc-file|XDC file here]].
 > >
 >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}}