Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| learn:software:tutorials:verilog-project-2:start [2021/05/14 23:06] – ↷ Links adapted because of a move operation Arthur Brown | learn:software:tutorials:verilog-project-2:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
|---|---|---|---|
| Line 10: | Line 10: | ||
| A list of the previous projects can be found [[learn/ | A list of the previous projects can be found [[learn/ | ||
| - | //This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[http://store.digilentinc.com/fpga-programmable-logic/ | + | //This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[https://digilent.com/shop/boards-and-components/ |
| ===== Some Background Information ===== | ===== Some Background Information ===== | ||
| - | The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, ' | + | The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, ' |
| ===== Relooking at the Simple Example HDL ===== | ===== Relooking at the Simple Example HDL ===== | ||
| Line 72: | Line 72: | ||
| > | > | ||
| - | > 7) After clicking next on the IP cores since we don't have any to add, click '' | + | > 7) After clicking next on the IP cores since we don't have any to add, click '' |
| > | > | ||
| > | > | ||
| Line 115: | Line 115: | ||
| > | > | ||
| - | > 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there' | + | > 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there' |
| > | > | ||
| > | > | ||
| Line 186: | Line 186: | ||
| But why restrict ourselves to a single input and a single output? Perhaps instead we want create a '' | But why restrict ourselves to a single input and a single output? Perhaps instead we want create a '' | ||
| - | As I am using the [[http://store.digilentinc.com/ | + | As I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/ |
| This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. | This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. | ||

