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learn:software:tutorials:verilog-project-2:start [2017/01/27 19:15] – James Colvinlearn:software:tutorials:verilog-project-2:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 A list of the previous projects can be found [[learn/software/tutorials/verilog-projects/start|here]]. A list of the previous projects can be found [[learn/software/tutorials/verilog-projects/start|here]].
  
-//This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[http://store.digilentinc.com/fpga-programmable-logic/system-boards/|Digilent system boards]]. However, the project can be easily modified to accommodate different types of external inputs (buttons instead of switches) or to use external I/O components rather than embedded components. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//+//This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[https://digilent.com/shop/boards-and-components/system-boards/|Digilent system boards]]. However, the project can be easily modified to accommodate different types of external inputs (buttons instead of switches) or to use external I/O components rather than embedded components. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//
  
 ===== Some Background Information =====  ===== Some Background Information ===== 
-The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[learn/software/tutorials/vivado-xdc-file|XDC file]]) +The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[programmable-logic:guides:vivado-xdc-file|XDC file]]) 
  
 ===== Relooking at the Simple Example HDL =====  ===== Relooking at the Simple Example HDL ===== 
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 >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}}
  
-> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[learn/software/tutorials/vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/|Arty]], I used the Master XDC available on it's [[reference/programmable-logic/arty/start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.+> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[programmable-logic:guides:vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty]], I used the Master XDC available on it's [[programmable-logic:arty:start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.
 > >
 >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}}
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 >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}}
  
-> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[learn/software/tutorials/vivado-xdc-file|XDC file here]].+> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[programmable-logic:guides:vivado-xdc-file|XDC file here]].
 > >
 >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}}
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 >{{:learn:software:tutorials:verilog-project-2:choose_auto_connect.png?600|Auto connect to your FPGA after it is connected (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:choose_auto_connect.png?600|Auto connect to your FPGA after it is connected (click to enlarge)}}
  
-You'll then be asked to choose the bitstream file (we don't have a debug core in our code, so we won't put anything in that field) 
 > 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field. > 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field.
 > >
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 But why restrict ourselves to a single input and a single output? Perhaps instead we want create a ''bus'' of inputs and outputs (like an array in a C/C++ environment) so we can try out some more complex (but still simple) combinatorial logic. But why restrict ourselves to a single input and a single output? Perhaps instead we want create a ''bus'' of inputs and outputs (like an array in a C/C++ environment) so we can try out some more complex (but still simple) combinatorial logic.
  
-As I am using the [[http://store.digilentinc.com/arty-artix-7-fpga-development-board-for-makers-and-hobbyists/|Arty board]] which has four embedded switches and four mono-color LEDs (as well as four tri-color LEDs if I want to use them) I can easily use up to a 4-bit bus for my inputs and outputs. Your FPGA board may have a different number or a different type of available inputs and outputs, or perhaps you need to use some external components to get some physical inputs and outputs. If I took advantage of some external components, I could theoretically create as large of a bus as I wanted, but that is beyond the scope of this project.  We won't be going through every step like we did the first time, although some key screenshots will be shown as a reference point for your convenience. //Remember, If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//+As I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty board]] which has four embedded switches and four mono-color LEDs (as well as four tri-color LEDs if I want to use them) I can easily use up to a 4-bit bus for my inputs and outputs. Your FPGA board may have a different number or a different type of available inputs and outputs, or perhaps you need to use some external components to get some physical inputs and outputs. If I took advantage of some external components, I could theoretically create as large of a bus as I wanted, but that is beyond the scope of this project.  We won't be going through every step like we did the first time, although some key screenshots will be shown as a reference point for your convenience. //Remember, If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//
  
 This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions.  This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. 
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 ===== Important Takeaways from Project 2 ===== ===== Important Takeaways from Project 2 =====
-  * +  * Creating single bit and multi-bit inputs and outputs 
 +  * Assigning input ports to output ports for single bits, bits within bus's, and bus's to bus's 
 +  * Confidence in going through the Vivado design flow from creating a project, editing it, and programming the system board
  
-tags to be added after I add in curly braces in the code below\\ 
-''tag> learn programmable-logic software tutorials vivado verilog''