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learn:software:tutorials:verilog-project-2:start [2017/01/17 23:04] – James Colvinlearn:software:tutorials:verilog-project-2:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Verilog® HDL: Project 2 ====== ====== Verilog® HDL: Project 2 ======
 +
 ===== Using switches to control LEDs ===== ===== Using switches to control LEDs =====
  
 ===== Project Overview ===== ===== Project Overview =====
-The goal of this project is to take the [[learn/software/tutorials/verilog-project-1/start#A_simple_Example|simple example from Project 1]] and program our FPGA with it so that we can control a single LED with a single switch. Then, we'll take the same program and expand it to have multiple switches control multiple LEDs. Brave users will be challenged (with some guidance) at the end to do the same thing with some external components. If you have not already installed Vivado, you can find a guide to do so [[learn/software/tutorials/vivado-install-guide/start|here]]. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the [[vivado/getting_started/start|Getting Started with Vivado Guide]].+The goal of this project is to take the [[learn/software/tutorials/verilog-project-1/start#A_simple_Example|simple example from Project 1]] and program our FPGA with it so that we can control a single LED with a single switch. Then, we'll take the same program and expand it to have multiple switches control multiple LEDs. Brave users will be challenged at the end to do the same thing with some external components. If you have not already installed Vivado, you can find a guide to do so [[learn/software/tutorials/vivado-install-guide/start|here]]. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the [[vivado/getting_started/start|Getting Started with Vivado Guide]].
  
 A list of the previous projects can be found [[learn/software/tutorials/verilog-projects/start|here]]. A list of the previous projects can be found [[learn/software/tutorials/verilog-projects/start|here]].
  
-//This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[http://store.digilentinc.com/fpga-programmable-logic/system-boards/|Digilent system boards]]. However, the project can be easily modified to accommodate different types of external inputs (buttons instead of switches) or to use external I/O components rather than embedded components. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//+//This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[https://digilent.com/shop/boards-and-components/system-boards/|Digilent system boards]]. However, the project can be easily modified to accommodate different types of external inputs (buttons instead of switches) or to use external I/O components rather than embedded components. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//
  
 ===== Some Background Information =====  ===== Some Background Information ===== 
-The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[learn/software/tutorials/vivado-xdc-file|XDC file]]) +The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[programmable-logic:guides:vivado-xdc-file|XDC file]]) 
  
 ===== Relooking at the Simple Example HDL =====  ===== Relooking at the Simple Example HDL ===== 
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 ===== Programming our FPGA ===== ===== Programming our FPGA =====
  
-> 0) If you haven't already done so, go ahead and open up Vivado to the first screen and click on the "Create New Project" button. If you've gone through the [[vivado/getting_started/start|Getting Started with Vivado Guide]] already, a lot of this will be very familiar to you (or near identical). You can follow along if you like, or if you feel that you can get your board programmed by yourself without the guide, feel free to do so (just to confirm you've got it right), and then [[learn/software/tutorials/verilog-project-2/start#mulitple_switches_and_leds|jump down]] to the multiple switches and LEDs section.+> 0) If you haven't already done so, go ahead and open up Vivado to the first screen and click on the "Create New Project" button. If you've gone through the [[vivado/getting_started/start|Getting Started with Vivado Guide]] already, a lot of this will be very familiar to you (or near identical). You can follow along if you like, or if you feel that you can get your board programmed by yourself without the guide, feel free to do so (just to confirm you've got it right), and then __[[:learn:software:tutorials:verilog-project-2:start#multiple_switches_and_LEDS|jump down]]__ to the multiple switches and LEDs section.
  
 > 1) On the opening screen, click on the ''Create New Project'' button. > 1) On the opening screen, click on the ''Create New Project'' button.
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 >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}}
  
-> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[learn/software/tutorials/vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/|Arty]], I used the Master XDC available on it's [[reference/programmable-logic/arty/start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.+> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[programmable-logic:guides:vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty]], I used the Master XDC available on it's [[programmable-logic:arty:start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.
 > >
 >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}}
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 >{{:learn:software:tutorials:verilog-project-2:we_can_edit_the_verilog_module_now.png?600|Let's edit the Verilog module (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:we_can_edit_the_verilog_module_now.png?600|Let's edit the Verilog module (click to enlarge)}}
  
-> 15) Now we just need to add the functionality of how our circuit module we are creating on the FPGA that has a single input and a single output is going to work. This is done between the ''};'' in the module declaration(instantiation :?:) and the keyword ''endmodule''. For this project, we just want to have the state of the output (the LED) be the same as the state of the input (the switch), so we will use an ''assign'' statement to assign the state of the LED to be equal to the state of the switch via the following line of code:+> 15) Now we just need to add the functionality of how our circuit module we are creating on the FPGA that has a single input and a single output is going to work. This is done by declaring our inputs and outputs between the ''};'' in the module and the keyword ''endmodule''. For this project, we just want to have the state of the output (the LED) be the same as the state of the input (the switch), so we will use an ''assign'' statement to assign the state of the LED to be equal to the state of the switch via the following line of code:
 >''assign led = sw;'' >''assign led = sw;''
 +> Press Cntl+S to save your changes.
 > >
 >{{:learn:software:tutorials:verilog-project-2:verilog_module_is_edited.png?600|The Verilog module has been edited (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:verilog_module_is_edited.png?600|The Verilog module has been edited (click to enlarge)}}
  
  
-> 16) Now we'll edit our constraints file. We can find our copy of the XDC in the sources window in the ''Constraints''->''constrs_1''. Double click on it to open it in the workspace window.+> 16) Now we'll edit our constraints file. We can find our copy of the XDC in the sources window in the ''Constraints''->''constrs_1'' folder. Double click on it to open it in the workspace window.
 > >
 >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}}
  
-> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[learn/software/tutorials/vivado-xdc-file|XDC file here]].+> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[programmable-logic:guides:vivado-xdc-file|XDC file here]].
 > >
 >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}}
  
-> 18) +> 18) The two lines I will uncomment in this project will be the line corresponding to the first switch (labeled SW0 on the silk screen of the Arty) and the line corresponding to the first mono-color LED (labeled LD4 on the silk screen of the Arty). I renamed the switch (pin A8 on the FPGA) to sw and renamed the LED (pin H5 on the FPGA) to led. Press Cntr+S to save your changes.
 > >
 >{{:learn:software:tutorials:verilog-project-2:constraints_file_is_edited.png?600|We have edited the XDC (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:constraints_file_is_edited.png?600|We have edited the XDC (click to enlarge)}}
  
-click run synthesis,  +> 19) Click the ''Run Synthesis'' button on the Flow Navigator that is on the left hand side of the Vivado GUI.
-> 19) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:click_run_synthesis.png?600|Click run synthesis (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:click_run_synthesis.png?600|Click run synthesis (click to enlarge)}}
  
-choose synthesis options; This can take awhile since Vivado processes a ton of things hidden to the user and works with the entire FPGA and not just what we are utilizing, so you'll probably want to maximize the number of jobs (computer cores Vivado is allowed to use) unless you plan to be doing a lot of other things simultaneously. For some of the larger projects we get into (which are still examples in the end) the synthesizing, implementing, and generating bitstream procedure can take upwards of 30 minutes if your computer isn't very fast. +> 20) A wizard will pop up that will allow you to choose your synthesis options. You'll want to have your project launch in the local directory and run on the local host (as opposed to only generating scripts. 
-> 20) +> As a side note, the whole combination of synthesis, implementation, and the generation of the bitstream to program the FPGA can take a bit of time (i.e. more than 10 minutes in some cases) since Vivado processes a ton of things hidden to the user and works with the entire FPGA and not just what we are utilizing, so you will probably want to maximize the number of jobs (computer cores Vivado is allowed to use) unless you plan to be doing a lot of other things simultaneously.  
 +> When you are happy with your selections, click ''OK''.
 > >
 >{{:learn:software:tutorials:verilog-project-2:run_synthesis_options.png?600|Choose your synthesis optimizations (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:run_synthesis_options.png?600|Choose your synthesis optimizations (click to enlarge)}}
  
-synthesis running (about 30 seconds for me with 4 cores on an SSD) +> 21) After you click ok, you'll need to wait for the synthesis to finish running, which may take a minute or two depending on how fast your computer runs.
-> 21) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:running_synthesis.png?600|Wait for the synthesis to finish running (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:running_synthesis.png?600|Wait for the synthesis to finish running (click to enlarge)}}
  
-click run implementation on the wizard that pops up, can choose how many cores you use again if you haven't clicked the don't show this dialog again. +> 21) Click ''Run Implementation'' on the next wizard that pops up and then click ''Ok''. You can again choose how many tasks (cores your computer uses) if you didn't click on the "don't show this dialog" box last time.
-> 21) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:click_run_implementation.png?600|Run the implementation (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:click_run_implementation.png?600|Run the implementation (click to enlarge)}}
  
-implementation running (45 seconds for me with 4 cores on an SSD) +> 22) After you click ok, you'll need to wait for the implementation to finish running, which may take a minute or two depending on how fast your computer runs.
-> 22) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:running_implementation.png?600|Wait for the implementation to finish running (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:running_implementation.png?600|Wait for the implementation to finish running (click to enlarge)}}
  
-click generate bitstream on the wizard (don't necessarily want to click the ''don't show this dialog again'' here because if you are designing something on your own, you may want to just check to see if something got that far in the process or if theres already an error, not bother generating a bitstream for it), choose number of jobs/cores again +> 23) Another wizard will pop up where you will want to click ''Generate Bitstream''.  
-> 23) +> As a side note, you may not necessarily want to click the ''don't show this dialog again'' box this time because if you are designing a circuit for your FPGA to run, you may just want to check to see if Vivado was able to successfully able to make it through synthesis and implementation. If there is a warning or error, you would not want to generate a faulty bitstream. 
 +> After this screen you will be able to choose some bitstream generation options, much like for synthesis and implementation. When you are happy with your selections, click ''Ok''.
 > >
 >{{:learn:software:tutorials:verilog-project-2:click_generate_bitstream.png?600|Click generate bitstream (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:click_generate_bitstream.png?600|Click generate bitstream (click to enlarge)}}
  
-generate bitstream running (30 seconds for me with 4 cores on an SSD) +> 24) After you click ok, you'll need to wait for the bitstream generation to finish running, which may take a minute or two depending on how fast your computer runs.
-> 24) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:running_generate_bitstream.png?600|Wait for the bitstream generation to finish running (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:running_generate_bitstream.png?600|Wait for the bitstream generation to finish running (click to enlarge)}}
  
-click open hardware manager on the wizard and then click ''Ok''. +> 25) Click ''Open Hardware Manager'' on the wizard that pops up and then click ''Ok''.
-> 25) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:click_open_hardware_manager.png?600|Open the hardware manager (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:click_open_hardware_manager.png?600|Open the hardware manager (click to enlarge)}}
  
-if your FPGA is not connected already, you'll see a ''no hardware target is open'' message at the top.  +> 26) If your FPGA is not connected to your computer already via a micro-USB cable, you'll see a ''no hardware target is open'' message at the top of the screen. Go ahead and click on the ''Open Target'' text that is next to the message.
-> 26) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:no_hardware_target_is_open.png?600|No hardware target is open if your FPGA is not connected yet (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:no_hardware_target_is_open.png?600|No hardware target is open if your FPGA is not connected yet (click to enlarge)}}
  
-You'll be able to click the ''open target'' screen and choose auto connect if you have connected your FPGA (make sure the power LEDs on the FPGA turn on when you connect it to your computer via the micro USB cable (if you are using a Digilent board) +> 27) Make sure your FPGA is connected to your computer (and that the power LEDs on the FPGA turn on when it is connected to your computer) and then choose ''Auto Connect'' on the menu that appears after you click on ''Open Target''.
-> 27) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:choose_auto_connect.png?600|Auto connect to your FPGA after it is connected (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:choose_auto_connect.png?600|Auto connect to your FPGA after it is connected (click to enlarge)}}
  
-You'll then be asked to choose the bitstream file (we don't have a debug core in our code, so we won't put anything in that field) +> 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field.
-> 28) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:choose_bitstream_file.png?600|Let's choose a bitstream to program the FPGA with (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:choose_bitstream_file.png?600|Let's choose a bitstream to program the FPGA with (click to enlarge)}}
  
-The bitstream file itself is a little unintuitive to find. You can find it by opening up the folder where you told Vivado to initially save your project, go to <projectName>.runs, then impl_1, and then choose the .bit that you see. I named my overall Verilog module top.v, so the bit file is ''top.bit''. then click ''Ok'' +> 29) The bitstream file itself is a little unintuitive to find. You can find it by opening up the folder where you told Vivado to initially save your project, go to ''<projectName>.runs'', then ''impl_1'', and then choose the ''.bit'' that you see. I named my overall Verilog module top.v, so the bit file is ''top.bit''. Then click ''Ok''.
-> 29) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:bitstream_file_location.png?600|Where is the Vivado bitstream file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:bitstream_file_location.png?600|Where is the Vivado bitstream file (click to enlarge)}}
  
-click ''program''; this takes under 10 seconds for any computer, so it's not too bad.  +> 30) Finally, we can click ''Program''; the actually programming process takes under 10 seconds for any computer, so it's not too bad of a wait.
-> 30) +
 > >
 >{{:learn:software:tutorials:verilog-project-2:click_program.png?600|Program the FPGA (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:click_program.png?600|Program the FPGA (click to enlarge)}}
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 Now we're done! The way this project was setup, the first switch (labeled ''SW0'' on the Arty) controls the status of the first LED (labeled ''LD4'' on the Arty). Now we're done! The way this project was setup, the first switch (labeled ''SW0'' on the Arty) controls the status of the first LED (labeled ''LD4'' on the Arty).
  
- +{{:learn:software:tutorials:verilog-project-2:switch_to_led_demo.png?600|An image of the above demo in action (click to enlarge)}}
-need to make this look pretty rather than crazy with the picture labels and orientation. Perhaps I should do the whole picture captions beneath the image and the steps 1.1) with the arrows >... bother FIXME+
  
 ==== Multiple Switches and LEDs ==== ==== Multiple Switches and LEDs ====
 +But why restrict ourselves to a single input and a single output? Perhaps instead we want create a ''bus'' of inputs and outputs (like an array in a C/C++ environment) so we can try out some more complex (but still simple) combinatorial logic.
 +
 +As I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty board]] which has four embedded switches and four mono-color LEDs (as well as four tri-color LEDs if I want to use them) I can easily use up to a 4-bit bus for my inputs and outputs. Your FPGA board may have a different number or a different type of available inputs and outputs, or perhaps you need to use some external components to get some physical inputs and outputs. If I took advantage of some external components, I could theoretically create as large of a bus as I wanted, but that is beyond the scope of this project.  We won't be going through every step like we did the first time, although some key screenshots will be shown as a reference point for your convenience. //Remember, If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//
 +
 +This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. 
 +
 +> 1) The same process of a creating a Vivado project was followed; a top module was created, no IP was added, and the Master XDC file was copied into the local directory. Once we confirm our project settings, we can then create our new module with buses on the module wizard that appears. For each input or output that you want to be a bus, check the ''bus'' box and indicate the size of the bus through the ''MSB'' and ''LSB'' options.
 +>
 +>{{:learn:software:tutorials:verilog-project-2:creating_a_module_with_a_bus.png?600|Creating a bus through the module wizard (click to enlarge)}}
 +
 +> 2) Once the corresponding Verilog module has been created, we can ''assign'' individual values within each bus to other individual values. As you might expect, you cannot ''assign'' a whole bus to a single input or output, but can perform some logical operations, such as the logical negation or ''!'' operator.
 +> 
 +>{{:learn:software:tutorials:verilog-project-2:assigning_individual_values_in_a_bus.png?600|Assign individual values inside of a bus (click to enlarge)}}
 +
 +> 3) The XDC file will also need to be edited so that Vivado knows which FPGA pins we intend to use. With this Master XDC file, the names of the pins for both the switches (shown) and the LEDs (not shown in the image) are already named in such a way so that they match the names used in our Verilog module. You could change the names in both the module and the XDC file to something else, but why do more work if it is already legible?
 +>
 +>{{:learn:software:tutorials:verilog-project-2:part_of_the_xdc_file_for_our_bus_inputs.png?600|What part of the XDC file will look like for the bus inputs and outputs (click to enlarge)}}
 +
 +> 4) Here's what the Arty looks like with SW0 switched "on" and SW1 switched "off".
 +>
 +> {{learn:software:tutorials:verilog-project-2:2-bit_bus_demo.png?600|Image of the above demo in action (click to enlarge)}}
 +
 +> 5) It is also possible to assign a bus of outputs the value of a bus of inputs. The trick here is that you need to use the bit-wise negation operator, ''~'', rather than the logical negation operator, ''!'', which operates on the entire bus rather than bit by bit. The ''~'' operator will also work for single bits much like the example immediately above this one.
 +>
 +> {{learn:software:tutorials:verilog-project-2:bus_to_bus_module.png?600|Verilog Module assigning a bus of LEDs to the opposite state of a bus of switches (click to enlarge)}}
 +
 +> 6) Here's what the Arty looks like for the above code with SW3 switched "off" and switches SW0, SW1, and SW2 switched "on".
 +>
 +> {{learn:software:tutorials:verilog-project-2:bus_to_bus_demo.png?600|Image of the above demo in action (click to enlarge)}}
  
-The above assign statement gives the current value of sw (switch) to led (an LED). +==== Taking it one step further ==== 
-Because HDL in general (not just Verilog) describes an actual circuit that will  +Try using some of the external I/O rather than the embedded I/O on your system board. You can even keep the Verilog module code exactly the same; the key here will be to change the XDC file so that the pins you want to use instead (such as some Pmod Host port pins) match the names used in your port declarations in your Verilog module.
-be implemented onto the FPGA, rather than telling a processor what to do like in +
-a microcontroller which is limited by its internal clock that dictates the timing +
-the above statement that assigns the value of sw to led will essentially happen +
-in real time, or at least as fast as it takes the electricity to propgate from  +
-the switch to the FPGA and then directly to the LED. +
  
 ===== Important Takeaways from Project 2 ===== ===== Important Takeaways from Project 2 =====
-  * +  * Creating single bit and multi-bit inputs and outputs 
 +  * Assigning input ports to output ports for single bits, bits within bus's, and bus's to bus's 
 +  * Confidence in going through the Vivado design flow from creating a project, editing it, and programming the system board
  
-tags to be added after I add in curly braces in the code below\\ 
-''tag> learn programmable-logic sfotware tutorials vivado verilog''