Verilog® HDL: Project 1

The goal of this project is to type up our first Verilog project by ourselves inside of Vivado. If you have not already installed Vivado, you can find a guide to do so here. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the Getting Started with Vivado Guide.

A Verilog® module of a circuit encapsulates a description of its functionality as a structural or behavioral view of its input-output relationship. A structural view could be as simple as a netlist of gates or as complex as a high level architectural partition of the circuit into major functional blocks, such as an arithmetic and logic unit (ALU). A behavioral view could be a simple Boolean equation model, a register transfer level (RTL), or an algorithm. This tutorial will look at the basics of a Verilog file.

The general format for a Verilog® circuit description is shown in the code in the picture below. Major keywords have been shown in blue, comments in green, Verilog requirements in pick, and key text strings the user must supply are shown in bolded italics.

insert image here

This timescale is required for all Verilog projects to synthesize correctly. If you had multiple types of delays, multiple timescales may be listed.

In a schematic capture environment, a graphical symbol defines a given logic circuit by showing a “bounding box” as well as input and output connections. In Verilog, this same concept is used, only the bounding box must be explicitly typed into the text editor, starting with “module” and ending with the phrase “endmodule”.

The module block (as shown in the image) gives the circuit a name (“led_sw” for readibility, it could have been called “myFirstModule123abc”) and defines all input and output ports, effectively playing the same role as a symbol in a schematic environment. The module is closed by an “endmodule” statement, and all the statement between module declaration and “endmodule” describes the functionality of the module, i.e., the internal circuit connection of the module.

Whenever you are writing a Verilog module, the first thing to do is to define the input and output signals. In the example in Fig. 1, there is one input signal “sw” coming from the onboard switch SW0, and one output signal “led” connected to LED0. How did we choose the names “sw” and “led”? They came from the XDC file. need link to XDC file page description

Note, however, that input and output can be a group of wires as well. We call these groupings a bus. To declare the input or output as a bus, we need to provide the CAD tools with the index of the most significant bit (MSB) of the bus and the index of the least significant bit (LSB) of the bus. For example, the following code defines an 8-bit wide bus “sw”, where the left-most bit (MSB) has the index 7 and the right-most bit (LSB) has the index 0.

  input [7:0] sw  

Indexing a bus in Verilog is similar to indexing an array in the C language. For example, if we want to index the second bit of sw bus declared above, we will use sw[1].

The assign statement in the example above assigns the signal value on the net “sw” to the net “led”. In implementation, it creates a wire that connects the input port sw to the output port led.

An assign statement can also be used to assign one signal of a bus to one signal of another bus. For example, if we declared sw as an 8-bit wide bus and LED as an 8-bit wide bus, and we want to use second switch to control fourth LED, the code will be:

module led_sw(
output [7:0] led,
input [7:0] sw
);
assign led[3] = sw[1];
...
endmodule

You can also assign a constant number to a signal or a bus to tie them to either logic '1' (VDD) or logic '0' (GND). The basic syntax for a constant number in Verilog is:

<Width in bits>'<base letter><number>

For example:

• Module in Verilog HDL acts like the bounding box in circuit schematic.
• Bus is a group of signals (wires).
• Assign statement passes the value of a signal/bus to another signal/bus.
• Constant in Verilog HDL is presented in form of <Width in bits>'<base letter><number>

tags to be added via the tag> and double curly braces around everything
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