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learn:software:tutorials:verilog-project-1:start [2017/01/17 18:41] – James Colvinlearn:software:tutorials:verilog-project-1:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ==== Input, Output, and Bus ==== ==== Input, Output, and Bus ====
 Whenever you are writing a Verilog module, the first thing to do is to define the input and output signals. In the example in Fig. 1, there is one input signal “sw” coming from the onboard switch SW0, and one output signal “led” connected to LED0. How did we choose the names "sw" and "led"?  Whenever you are writing a Verilog module, the first thing to do is to define the input and output signals. In the example in Fig. 1, there is one input signal “sw” coming from the onboard switch SW0, and one output signal “led” connected to LED0. How did we choose the names "sw" and "led"? 
-They came from the [[learn/software/tutorials/vivado-xdc-file|XDC file]]. +They came from the [[programmable-logic:guides:vivado-xdc-file|XDC file]]. 
  
 Note, however, that input and output can be a group of wires as well. We call these groupings a bus. To declare the input or output as a bus, we need to provide the CAD tools with the index of the most significant bit (MSB) of the bus and the index of the least significant bit (LSB) of the bus. For example, the following code defines an 8-bit wide bus “sw”, where the left-most bit (MSB) has the index 7 and the right-most bit (LSB) has the index 0, with a colon '':'' separating the two numbers. Note, however, that input and output can be a group of wires as well. We call these groupings a bus. To declare the input or output as a bus, we need to provide the CAD tools with the index of the most significant bit (MSB) of the bus and the index of the least significant bit (LSB) of the bus. For example, the following code defines an 8-bit wide bus “sw”, where the left-most bit (MSB) has the index 7 and the right-most bit (LSB) has the index 0, with a colon '':'' separating the two numbers.