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learn:software:tutorials:verilog-project-1:start [2017/01/11 01:15] – James Colvinlearn:software:tutorials:verilog-project-1:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ===== Project Overview ===== ===== Project Overview =====
-The goal of this project is to type up our first Verilog project by ourselves inside of Vivado. If you have not already installed Vivado, you can find a guide to do so [[learn/software/tutorials/vivado-install-guide/start|here]]. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the [[vivado/getting_started/start|Getting Started with Vivado Guide]].+The goal of this project is to learn about the components inside of a Verilog project (but not program an FPGA quite yet, that's the next project). If you have not already installed Vivado, you can find a guide to do so [[learn/software/tutorials/vivado-install-guide/start|here]]. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the [[vivado/getting_started/start|Getting Started with Vivado Guide]]. 
 + 
 +A list of the all of the Verilog projects can be found [[learn/software/tutorials/verilog-projects/start|here]]. 
 + 
 +//Remember that we won't be adding any files or creating a bitstream for this first project; that'll all start in [[learn/software/tutorials/verilog-project-2/start|Project 2]]. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//
  
 ===== What is a Verilog® Module? =====  ===== What is a Verilog® Module? ===== 
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 ===== A Simple Example =====  ===== A Simple Example ===== 
-The general format for a Verilog® circuit description is shown in the code in the picture below. Major keywords have been shown in blue, comments in green, Verilog requirements in pick, and key text strings the user must supply are shown in bolded italics.+The general format for a Verilog® circuit is shown in the code in the picture below. Major keywords have been shown in blue, comments in green, Verilog requirements in pick, and key text strings the user must supply are shown in bolded italics. We will then go through each of the lines in detail to learn about what they do.
  
 {{ :learn:software:tutorials:verilog-project-1:project_1_example.png?600 |A simple Verilog example}} {{ :learn:software:tutorials:verilog-project-1:project_1_example.png?600 |A simple Verilog example}}
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 ==== Module ==== ==== Module ====
-In a schematic capture environment, a graphical symbol defines a given logic circuit by showing a “bounding box” as well as input and output connections. In Verilog, this same concept is used, only the bounding box must be explicitly typed into the text editor, starting with "module" and ending with the phrase "endmodule". +In a schematic capture environment, a graphical symbol defines a given logic circuit by showing a “bounding box” as well as input and output connections. In Verilog, this same concept is used, only the bounding box must be explicitly typed into the text editor, starting with ''module'' and ending with the phrase ''endmodule''. 
  
-The module block (as shown in the image) gives the circuit a name ("led_sw" for readibility, it could have been called "myFirstModule123abc") and defines all input and output ports, effectively playing the same role as a symbol in a schematic environment. The module is closed by an “endmodule” statement, and all the statement between module declaration and “endmodule” describes the functionality of the module, i.e., the internal circuit connection of the module.+The module block (as shown in the image) gives the circuit a name ("led_sw" for readibility, it could have been called "myFirstModule123abc") and defines all input and output ports, effectively playing the same role as a symbol in a schematic environment. The module is closed by an ''endmodule'' statement, and all the statement between module declaration and ''endmodule'' describes the functionality of the module, i.e., the internal circuit connection of the module.
  
-In terms of syntax, the inputs and outputs of the named module are enclosed by a set of parenthesis '()' with a semicolon ';', with a comma ',' between each set of inputs/outputs. If a set of inputs/outputs is actually a bus (an array), a set of square brackets '[]' is used around a range of numbers in the form [MSB:LSB]. No special syntax is needed to end the module, just the word "endmodule".+In terms of syntax, the inputs and outputs of the named module are enclosed by a set of parenthesis ''()'' with a semicolon '';'' and with a comma '','' between each set of inputs/outputs. An example is provided below: 
 +<code> 
 +module inputOutput( 
 +input inputExample, 
 +output outputExample, 
 +input [2:0] 3inputs, 
 +output [7:0] 7outputs 
 +); 
 +endmodule 
 +</code> 
 +If a set of inputs/outputs is actually a bus (an array), a set of square brackets ''[]'' is used around a range of numbers in the form [MSB:LSB]. No special syntax is needed to end the module, just the word ''endmodule''.
  
 ==== Input, Output, and Bus ==== ==== Input, Output, and Bus ====
 Whenever you are writing a Verilog module, the first thing to do is to define the input and output signals. In the example in Fig. 1, there is one input signal “sw” coming from the onboard switch SW0, and one output signal “led” connected to LED0. How did we choose the names "sw" and "led"?  Whenever you are writing a Verilog module, the first thing to do is to define the input and output signals. In the example in Fig. 1, there is one input signal “sw” coming from the onboard switch SW0, and one output signal “led” connected to LED0. How did we choose the names "sw" and "led"? 
-They came from the XDC file. __//need link to XDC file page description//__+They came from the [[programmable-logic:guides:vivado-xdc-file|XDC file]]. 
  
-Note, however, that input and output can be a group of wires as well. We call these groupings a bus. To declare the input or output as a bus, we need to provide the CAD tools with the index of the most significant bit (MSB) of the bus and the index of the least significant bit (LSB) of the bus. For example, the following code defines an 8-bit wide bus “sw”, where the left-most bit (MSB) has the index 7 and the right-most bit (LSB) has the index 0, with a colon ':' separating the two numbers.+Note, however, that input and output can be a group of wires as well. We call these groupings a bus. To declare the input or output as a bus, we need to provide the CAD tools with the index of the most significant bit (MSB) of the bus and the index of the least significant bit (LSB) of the bus. For example, the following code defines an 8-bit wide bus “sw”, where the left-most bit (MSB) has the index 7 and the right-most bit (LSB) has the index 0, with a colon '':'' separating the two numbers.
  
 <code>  input [7:0] sw  </code> <code>  input [7:0] sw  </code>
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 ==== Assign ==== ==== Assign ====
-The assign statement in the example above assigns the signal value on the net “sw” to the net “led”. In implementation, it creates a wire that connects the input port sw to the output port led.+The ''assign'' statement in the example above assigns the signal value on the net “sw” to the net “led”. In implementation, it creates a wire that connects the input port sw to the output port led.
  
-An assign statement can also be used to assign one signal of a bus to one signal of another bus. For example, if we declared sw as an 8-bit wide bus and LED as an 8-bit wide bus, and we want to use second switch to control fourth LED, the code will be:+An ''assign'' statement can also be used to assign one signal of a bus to one signal of another bus. For example, if we declared sw as an 8-bit wide bus and LED as an 8-bit wide bus, and we want to use second switch to control fourth LED, the code will be:
  
 <code> <code>
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 </code> </code>
  
-At the end of each assign statement (can be more than one line long), a semicolon ';' is required.+At the end of each assign statement (can be more than one line long), a semicolon '';'' is required.
 ==== Constants ==== ==== Constants ====
 You can also assign a constant number to a signal or a bus to tie them to either logic '1' (VDD) or logic '0' (GND). The basic syntax for a constant number in Verilog is (including the apostrophe): You can also assign a constant number to a signal or a bus to tie them to either logic '1' (VDD) or logic '0' (GND). The basic syntax for a constant number in Verilog is (including the apostrophe):
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   * Assign statement passes the value of a signal/bus to another signal/bus.   * Assign statement passes the value of a signal/bus to another signal/bus.
   * Constant in Verilog HDL is presented in form of <Width in bits>'<base letter><number>   * Constant in Verilog HDL is presented in form of <Width in bits>'<base letter><number>
 +  * A desire to check out [[learn/software/tutorials/verilog-project-2/start|Project 2]] where we actually program the FPGA
  
  
 tags to be added via the tag> and double curly braces around everything\\ tags to be added via the tag> and double curly braces around everything\\
 learn programmable-logic software tutorial vivado learn programmable-logic software tutorial vivado