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learn:programmable-logic:tutorials:zedboard-creating-custom-ip-cores:start [2016/07/25 23:52] – jon peyronlearn:programmable-logic:tutorials:zedboard-creating-custom-ip-cores:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ---- ----
 =====Prerequisites===== =====Prerequisites=====
-- Completed the Zedboard [[https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-getting-started-with-zynq/start|Getting Started with Zynq]]+- Completed the Zedboard [[/learn/programmable-logic/tutorials/zedboard-getting-started-with-zynq/start|Getting Started with Zynq]]
 - Have SDK installed - Have SDK installed
  
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    );    );
 </code> </code>
 +====6. Packaging the IP core====
 +Now that we have written the core, it is time to package up the HDL to create a complete IP package.
  
 +>6.1) Now click on **Package IP** in the Flow Navigator and you should see the Package IP tab. Select **Compatibility** and make sure "Artix7" and "Zynq" are present. If those are not there, you can add them by clicking the plus button. The Life Cycle does not matter at this point.
 +>
 +>{{:zybo:zybo:image_47.png?nolink&500|}}
 +
 +
 +>6.2) Select **Customization Parameters** and select the line for **Merge Changes from Customization Parameters Wizard**. This will add the PWM_COUNTER_MAX parameter from the top file under the hidden parameters folder.
 +>
 +>{{:zybo:zybo:image_48.png?nolink&800|}}
 +
 +>6.3) Select **Customization GUI**. This is were we get to change our graphical interface. One problem, there is not a window for our parameter. Right-click **Pwm Counter Max** and select **Edit Parameter...**. Check the box next to **Visible in Customization GUI**. Check the **Specify Range** box. Select **Range of Integers** from the **Type** drop-down menu. Since we have a max value of (2^16)-1 = 65535 and a min value of 0, then Click **Ok**.
 +>
 +>{{:zybo:zybo-6.3-edit-ip-param.png?nolink&800|}}
 +
 +>6.4) Drag the **Pwm Counter Max** into **Page 0** to get it in the main page.
 +>
 +>{{:zybo:zybo:image_49.png?nolink&800|}}
 +
 +
 +>6.5) Now the core should be complete so select **Review and Package** and click the **Re-package IP** button.
 +>
 +>{{:zybo:zybo:image_50.png?nolink&800|}}
 +
 +
 +>6.6) A popup will ask if you want to close the project, Select **Yes**.
 +>
 +>{{:zybo:zybo:image_18.png?nolink&500|}}
 +
 +----
 +
 +==== 7. Create Zynq design ====
 +>7.1) In the project manager page of the original window, click **Create Block Design**. This adds a block design to the project.
 +
 +>7.2) Use the {{:genesys2:addip.jpg?nolink|}} **Add IP** button to add the **Zynq Processing System**.
 +>
 +>{{:zybo:zybo:image_20.png?nolink&600|}}
 +
 +>7.3) Use the {{:genesys2:addip.jpg?nolink|}} **Add IP** button again to add our **PWM core**.
 +>
 +>{{:zybo:zybo:image_21.png?nolink&600|}}
 +
 +>7.4) **Run Block Automation**.
 +>
 +>{{:zybo:zybo:image_23.png?nolink&600|}}
 +>
 +>7.5) The connection automation tool will add the required logic blocks for the demo. Select **Run Connection Automation** highlighted in blue.
 +>
 +>{{:reference:programmable-logic:zedboard-getting-started-with-zynq:image_15.jpg?600|}}
 +>
 +>7.6) Your design should look like this:
 +>
 +>{{:zybo:zybo:image_26.png?nolink&600|}}
 +
 +>7.7) Double-click our **PWM core** to customize the parameter that we made earlier. Set the PWM Counter Max to 1024. and click **OK**.
 +>
 +>{{:zybo:zybo:image_32.png?nolink&600|}}
 +
 +>7.8) Right-click each of the PWM signals and select **Create Port...**
 +>
 +>{{:zybo:zybo:image_31.png?nolink&800|}}
 +
 +>7.9) Click the button for **Validate Design**.
 +>
 +>{{:zybo:zybo:image_33.png?nolink&800|}}
 +
 +>7.10) Click **Project Manager**, right-click the "design_1.db" file and **Create HDL Wrapper...**
 +>
 +>{{:zybo:zybo:image_35.png?nolink&600|}}
 +
 +>7.11) Double-click **design_1_wrapper.v** to open it in the editor. Take note of the name for the PWM signals. Add the "zedboard_master_XDC_RevC_D_v3.xdc" constraint file that can be downloaded from [[https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/|Avnet's Zedboard page]]. First comment all lines then uncomment the lines of code for the LEDs in the xdc file and change this:
 +><code>
 +      ## ----------------------------------------------------------------------------
 +      ## User LEDs - Bank 33
 +      ## ---------------------------------------------------------------------------- 
 +      set_property PACKAGE_PIN T22 [get_ports {LD0}];  # "LD0"
 +      set_property PACKAGE_PIN T21 [get_ports {LD1}];  # "LD1"
 +      set_property PACKAGE_PIN U22 [get_ports {LD2}];  # "LD2"
 +      set_property PACKAGE_PIN U21 [get_ports {LD3}];  # "LD3"
 +</code>
 +>To this:
 +><code>
 +      ## ----------------------------------------------------------------------------
 +      ## User LEDs - Bank 33
 +      ## ---------------------------------------------------------------------------- 
 +      set_property PACKAGE_PIN T22 [get_ports {PWM0}];  # "PWM0"
 +      set_property PACKAGE_PIN T21 [get_ports {PWM1}];  # "PWM1"
 +      set_property PACKAGE_PIN U22 [get_ports {PWM2}];  # "PWM2"
 +      set_property PACKAGE_PIN U21 [get_ports {PWM3}];  # "PWM3"
 +</code>
 +>Then uncomment the lines of code for bank 33 in the xdc file and change this:
 +><code>
 +      # Un-comment one or more of the following IOSTANDARD constraints according to
 +      # the bank pin assignments that are required within a design.
 +      # ---------------------------------------------------------------------------- 
 +
 +      # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. 
 +      #set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
 +</code>
 +>To this:
 +><code>
 +      # Un-comment one or more of the following IOSTANDARD constraints according to
 +      # the bank pin assignments that are required within a design.
 +      # ---------------------------------------------------------------------------- 
 +
 +      # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. 
 +      set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
 +</code>
 +
 +>7.12) Click **Generate Bitstream**. Building the bit file can take some time.
 +
 +>7.13) Export the hardware by going to **File->Export->Export Hardware...**
 +>
 +>{{:zybo:zybo:image_37.png?nolink&600|}}
 +
 +>7.14) Check the box **Include bitstream** and click **Ok**
 +>
 +>{{:zybo:zybo:image_38.png?nolink&400|}}
 +
 +>7.15) Select **File->Launch SDK**, and hit **Ok** on the window that pops up.
 +>
 +>{{:zybo:zybo:image_39.png?nolink&600|}}
 +
 +----
 +====8. Programming in SDK ====
 +>8.1) Create a new application project
 +>
 +>{{:zybo:zybo:image_41.png?nolink&600|}}
 +
 +
 +>8.2) Setup the window as shown below and then click **Next** 
 +>
 +>{{:learn:programmable-logic:tutorials:zedboard-creating-custom-ip-cores:image_15.jpg?600|}}
 +>
 +>8.3) Select **Empty Application** and then click **Finish**.
 +>
 +>{{:learn:programmable-logic:tutorials:zedboard-creating-custom-ip-cores:image_13.jpg?600|}}
 +>
 +>8.4) Expand the **PWM_AXI_tutorial->src** folder. Right-click the **src** folder and **add a new file**. Create a file named "main.c".
 +>
 +>{{:zybo:zybo:image_63.png?nolink&600|}}
 +
 +>8.5) Add the lines:
 +><code>
 +#include "xparameters.h"
 +#include "xil_io.h"
 +
 +//#define MY_PWM XPAR_MY_PWM_CORE_0_S00_AXI_BASEADDR //Because of a bug in Vivado 2015.3 and 2015.4, this value is not correct.
 +#define MY_PWM 0x43C00000 //This value is found in the Address editor tab in Vivado (next to Diagram tab)
 +
 +int main(){
 +    int num=0;
 +    int i;
 +
 +    while(1){
 +        if(num == 1024)
 +             num = 0;
 +        else
 +             num++;
 +
 +        Xil_Out32(MY_PWM, num);
 +        Xil_Out32((MY_PWM+4), num);
 +        Xil_Out32((MY_PWM+8), num);
 +        Xil_Out32((MY_PWM+12), num);
 +
 +        for(i=0;i<300000; i++);
 +    }
 +}
 +</code>
 +
 +>8.6) To program the FPGA, Go to **Xilinx Tools->Program FPGA**. To load the SDK application onto the Zedboard, right-click on "PWM_AXI_tutorial" and select **Run As->Launch on Hardware (System Debugger)**.
 +>
 +>{{:learn:programmable-logic:tutorials:zedboard-creating-custom-ip-cores:image_14.jpg?600|}}
 +>
 +
 +
 +----
 +
 +====9. Celebrate!====
 +Now the 4 LEDs on the Zedboard will be pulsing.  Lean back in your chair and feel accomplished because you just created your own custom IP core.
 +{{tag>learn programmable-logic tutorial zedboard}}