Adding a Hierarchical Block to a Vivado IPI Design

• A Digilent FPGA development board.
• A computer with Vivado installed.
  • Following the Installing Vivado, Xilinx SDK, and Digilent Board Files guide will …
  • This guide was tested in Vivado 2019.2, other versions of Vivado can work, but support is not guaranteed.
• Familiarity with Vivado IP Integrator and a base block design to work from.
  • Following the Getting Started with Vivado IP Integrator guide will …

Download the master ZIP archive for Digilent's vivado-hierarchies repository and extract it.

Launch Vivado.

Open the Vivado Project you wish to use the Hierarchy in.

Open the project's Block Design.

In Vivado's TCL Console, enter the following command:

source (Archive extracted location)/(Hierarchy of choice)/create_hier.tcl

When the script is finished running, the block design will contain a Hierarchical Block with several IP inside of it. The IP will be connected to one another and to the block's ports and pins. The contents of the hierarchy can be viewed and changed by expanding it with the “+” button.

Make sure your design has a processor, and a peripheral that can be used for stdout. In the case of Microblaze, a UART IP must be connected to the board's USBUART interface. In the case of Zynq, the PS UART is used by default.

Check the README.txt file, found in your Pmod's folder in this repo, to find additional information about how the ports of the Hierarchy must be connected to the rest of your design. With this information in mind:

1. Connect all of the Hierarchy's AXI interfaces to the processor in your design by clicking on Run Connection Automation. and checking all appropriate boxes.
2. Connect any interrupts the Hierarchy may have to the appropriate interrupt controller, an AXI INTC IP (for Microblaze designs), the Zynq Processing System's irq_f2p port (for Zynq designs).
3. Connect any additional clocks to clocks generated by a Memory Interface Generator or a Clocking Wizard (for Microblaze designs), or a Zynq Processing System (for Zynq designs).

The next step, constraining the Hierarchy's Pmod_out port, has two different workflows.

If you selected a board while creating your project, you can use the Board Flow for this step:

Board Flow

1. Go to Vivado's Board tab and find the Pmod connector you wish to connect to the Hierarchy. Right click on the entry, typically named something like “Connector JA”, and select Connect Board Component. In the popup window, under Connect to existing IP, select the “Pmod_out” interface of the Hierarchy's Pmod Bridge IP. Click OK.
2. Make sure to validate your block design, save it, and create an HDL wrapper file.
3. Check the README.txt file in your Pmod's folder for additional instructions to determine whether any additional constraints are required.

If you selected a part instead of a board, or otherwise do not wish to use the Board Flow, you must create a port to connect to the Hierarchy's Pmod_out port and constrain its pins:

Manual Constraint Flow

1. Select the Pmod_out port, then right click on it and select Make External. Select the newly created external interface port (named something like “Pmod_out_0”) in the design, and give it a memorable name.
2. Validate your design, and save it. If your block design doesn't a wrapper file, right click on the design in the sources pane and select Create HDL Wrapper.
3. When the Hierarchy was created, a constraint file, named “(Default Hierarchy Name)_Pmod_out.xdc”, was imported into the project. This file contains the constraints required when not using the board flow. Uncomment each line starting with “set_property” by removing the leading “#” symbol.
4. The text “” appears in several places in the constraint file. These correspond to places where you will need to manually enter values specific to your board and design.
5. Find the correct port names for your Pmod interface by reviewing the port map of the top module near the top of the HDL wrapper file. Enter these port names into the corresponding place in the constraint file (after get_ports, near the end of each line).
6. Download the master XDC file for your board. Master XDC files for Digilent boards can be found in the digilent-xdc repository on Github. Find the LOC property values that correspond to the Pmod connector of your board that you wish to connect your Pmod to. Enter these values into the corresponding LOC fields in the hierarchy's constraint file.

Click Generate Bitstream. This process may take some time, depending on the complexity of the project.

Export the hardware design and bitstream to SDK by selecting File → Export → Export Hardware in the menu bar at the top of the window. In the resulting pop up window, check the Include bitstream box, then click OK.

Launch Xilinx SDK by selecting File → Launch SDK in the menu bar at the top of the window.

Create a new Application Project using the “Empty Application” template. Make sure to check if the Pmod requires you to change any settings or add any libraries to the project. Any requirements are detailed in the README.txt file in the Pmod's sdk_sources folder in this repo.

Copy all of the files from your Pmod's sdk_sources folder, then paste them into the empty application's src folder.

Make sure that the development board's programming mode select jumper is set to JTAG. Plug the board into the computer via it's microUSB “PROG” port and power it on.

Program the FPGA by selecting Xilinx → Program FPGA from the top menu bar.

Run the application project by right-clicking on the application project and selecting Run → Run on Hardware (System Debugger).