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| learn:programmable-logic:tutorials:pmod-ips:start [2021/06/09 00:31] – Arthur Brown | learn:programmable-logic:tutorials:pmod-ips:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ====== Getting Started with Digilent Pmod IPs ====== | ====== Getting Started with Digilent Pmod IPs ====== | ||
| - | |||
| - | <WRAP round important 660px> | ||
| - | === Important! === | ||
| - | This guide uses Vivado 2015.4 and will have outdated images with regards to newer versions of the Xilinx softare. See the [[learn/ | ||
| - | </ | ||
| {{: | {{: | ||
| ===== Overview ===== | ===== Overview ===== | ||
| + | <WRAP center round tip 60%> | ||
| + | Digilent Pmod IPs are only supported in Vivado and Xilinx SDK versions 2019.1 and earlier. | ||
| + | </ | ||
| Digilent provides several IPs that are designed to make implementing and using a Pmod on an FPGA as straightforward as possible. This guide will describe how to use a Pmod IP core in Vivado Microblaze or Zynq design. | Digilent provides several IPs that are designed to make implementing and using a Pmod on an FPGA as straightforward as possible. This guide will describe how to use a Pmod IP core in Vivado Microblaze or Zynq design. | ||
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| At the end of this tutorial you will have a Vivado design and demo for your FPGA or Zynq platform that uses a Digilent Pmod IP core. | At the end of this tutorial you will have a Vivado design and demo for your FPGA or Zynq platform that uses a Digilent Pmod IP core. | ||
| - | The following two dropdown tables show which platforms | + | The following two dropdown tables show which Digilent FPGA system boards |
| - | + | ||
| - | **Note**: //Issues have been reported regarding designs that include more than one instance of any one Pmod IP. For projects that require more than one of any one Pmod (for example, two Pmod NAVs), please use Vivado 2017.4.// | + | |
| --> Platforms Supported # | --> Platforms Supported # | ||
| - | ^ Platform | + | ^ Platform |
| - | | Arty | + | | [[programmable-logic: |
| - | | Arty S7 | Microblaze | + | | [[programmable-logic: |
| - | | Arty Z7 | Zynq | | + | | [[programmable-logic: |
| - | | Basys3 | + | | [[programmable-logic: |
| - | | Cmod A7 | Microblaze | + | | [[programmable-logic: |
| - | | Genesys2 | + | | [[programmable-logic: |
| - | | Nexys4 | + | | [[programmable-logic: |
| - | | Nexys4-DDR | + | | [[programmable-logic: |
| - | | Nexys Video | Microblaze | + | | [[programmable-logic: |
| - | | Zybo | + | | [[programmable-logic: |
| - | | Zybo Z7 | Zynq | | + | | [[programmable-logic: |
| + | | [[programmable-logic: | ||
| + | | [[programmable-logic: | ||
| + | | [[programmable-logic: | ||
| <-- | <-- | ||
| Line 48: | Line 47: | ||
| ^ AQS | ^ AQS | ||
| ^ BB | GPIO | ^ BB | GPIO | ||
| + | ^ BLE | ||
| ^ BT2 | ^ BT2 | ||
| ^ BTN | ^ BTN | ||
| ^ CAN | ^ CAN | ||
| ^ CLS | ^ CLS | ||
| - | ^ CMPS2 | + | ^ CMPS2 |
| ^ COLOR | ^ COLOR | ||
| ^ DA1 | ^ DA1 | ||
| Line 58: | Line 58: | ||
| ^ DPG1 | SPI | 50 | ext_spi_clk | ^ DPG1 | SPI | 50 | ext_spi_clk | ||
| ^ ENC | ^ ENC | ||
| + | ^ ESP32 | ||
| ^ GPS | ^ GPS | ||
| ^ GYRO | SPI | 50 | ext_spi_clk | ^ GYRO | SPI | 50 | ext_spi_clk | ||
| Line 85: | Line 86: | ||
| ----- | ----- | ||
| + | |||
| ===== Prerequisites ===== | ===== Prerequisites ===== | ||
| === Hardware === | === Hardware === | ||
| - | * **A Supported Digilent 7-Series FPGA or Zynq Board** | + | * **Supported Digilent 7-Series FPGA System |
| - | * **USB Cables** | + | * **MicroUSB Cable/s** |
| * **One or More Supported Digilent Pmods** | * **One or More Supported Digilent Pmods** | ||
| === Software === | === Software === | ||
| - | * **Xilinx Vivado | + | * **Xilinx Vivado |
| - | * //Vivado 2015.4 is used in this tutorial// | + | |
| * //Other versions of Vivado may work, but functionality is not guaranteed// | * //Other versions of Vivado may work, but functionality is not guaranteed// | ||
| - | * **Digilent Board Support Files** | + | |
| - | | + | |
| * **Digilent Vivado IP Library** | * **Digilent Vivado IP Library** | ||
| - | * [[https://github.com/ | + | * // |
| - | * // | + | |
| ----- | ----- | ||
| <WRAP round important 660px> | <WRAP round important 660px> | ||
| - | ===Important.=== | + | ===Important=== |
| If the Pmod IP to be used has a README file, be sure to review it before starting this tutorial. This file can be found in the **vivado-library/ | If the Pmod IP to be used has a README file, be sure to review it before starting this tutorial. This file can be found in the **vivado-library/ | ||
| </ | </ | ||
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| --> Microblaze # | --> Microblaze # | ||
| - | >Follow the [[/vivado/getting-started-with-ipi/start|Getting Started with Vivado IP Integrator]] tutorial to obtain a basic MicroBlaze block design. | + | >Follow the [[:vivado:getting-started-with-ipi:2018.2|Getting Started with Vivado IP Integrator]] tutorial to obtain a basic MicroBlaze block design. |
| > | > | ||
| > | > | ||
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| --> Zynq # | --> Zynq # | ||
| - | >Follow the **"Getting Started with Zynq" | + | >Follow the [[: |
| > | > | ||
| > | > | ||
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| >8.2) The bit file generation will begin. The tool will run // | >8.2) The bit file generation will begin. The tool will run // | ||
| > | > | ||
| - | >This process can take anywhere from **5 to 60 minutes** depending on your computer and target | + | >This process can take anywhere from **5 to 60 minutes** depending on the computer |
| >8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click **Cancel**. | >8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click **Cancel**. | ||
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| ====9. Export the Hardware Design to SDK==== | ====9. Export the Hardware Design to SDK==== | ||
| - | > | + | > |
| > | > | ||
| > | > | ||
| > | > | ||
| - | >A new file directory will be created in your project directory under **echo_server.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace. | + | >A new file directory will be created in the project directory under **echo_server.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace. |
| - | >9.2) On the main toolbar, click **File** and then **Launch SDK**. Leave both of the dropdown menus as their default //Local to Project// and click **OK**. This will open Xilinx SDK and import | + | >9.2) On the main toolbar, click **File |
| > | > | ||
| > | > | ||
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| ----- | ----- | ||
| - | ====10. | + | ====10. Xilinx SDK==== |
| - | >The HW design specification and included IP blocks are displayed in the //system.hdf// file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, | + | >The HW design specification and included IP blocks are displayed in the "system.hdf" |
| > | > | ||
| > | > | ||
| - | >Within the //Project Explorer// tab on the left, you can see your hardware platform. | + | >Within the //Project Explorer// tab on the left, you can see the hardware platform |
| - | >The drivers for the Pmod IP device | + | >The drivers for any Pmod IPs in the design |
| ----- | ----- | ||
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| ----- | ----- | ||
| - | {{tag> | + | {{tag> |