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| learn:programmable-logic:tutorials:pmod-ips:start [2018/01/19 23:37] – [2. Add the Digilent Library Repository] Arthur Brown | learn:programmable-logic:tutorials:pmod-ips:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ===== Overview ===== | ===== Overview ===== | ||
| + | <WRAP center round tip 60%> | ||
| + | Digilent Pmod IPs are only supported in Vivado and Xilinx SDK versions 2019.1 and earlier. | ||
| + | </ | ||
| Digilent provides several IPs that are designed to make implementing and using a Pmod on an FPGA as straightforward as possible. This guide will describe how to use a Pmod IP core in Vivado Microblaze or Zynq design. | Digilent provides several IPs that are designed to make implementing and using a Pmod on an FPGA as straightforward as possible. This guide will describe how to use a Pmod IP core in Vivado Microblaze or Zynq design. | ||
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| At the end of this tutorial you will have a Vivado design and demo for your FPGA or Zynq platform that uses a Digilent Pmod IP core. | At the end of this tutorial you will have a Vivado design and demo for your FPGA or Zynq platform that uses a Digilent Pmod IP core. | ||
| - | The following two dropdown tables show which platforms | + | The following two dropdown tables show which Digilent FPGA system boards |
| --> Platforms Supported # | --> Platforms Supported # | ||
| - | ^ Platform | + | ^ Platform |
| - | | Arty | + | | [[programmable-logic: |
| - | | Arty S7 | Microblaze | + | | [[programmable-logic: |
| - | | Arty Z7 | Zynq | No | | | + | | [[programmable-logic: |
| - | | Basys3 | + | | [[programmable-logic: |
| - | | Cmod A7 | Microblaze | + | | [[programmable-logic: |
| - | | Genesys2 | + | | [[programmable-logic: |
| - | | Nexys4 | + | | [[programmable-logic: |
| - | | Nexys4-DDR | + | | [[programmable-logic: |
| - | | Nexys Video | Microblaze | + | | [[programmable-logic: |
| - | | Zybo | + | | [[programmable-logic: |
| - | | Zybo Z7 | Zynq | + | | [[programmable-logic: |
| + | | [[programmable-logic: | ||
| + | | [[programmable-logic: | ||
| + | | [[programmable-logic: | ||
| <-- | <-- | ||
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| --> Pmods Supported # | --> Pmods Supported # | ||
| /*Please keep this table alphabetically sorted*/ | /*Please keep this table alphabetically sorted*/ | ||
| - | ^ Pmod ^ Interface Type ^ Reference clock frequency (MHz) ^ Reference Clock signal name ^ Interrupt pin name/ | + | ^ Pmod ^ Interface Type ^ Reference clock frequency (MHz) ^ Reference Clock signal name ^ Interrupt pin name/ |
| - | ^ 8LD | + | ^ 8LD |
| - | ^ ACL | + | ^ ACL |
| - | ^ ACL2 | SPI | 50 | ext_spi_clk | + | ^ ACL2 | SPI | 50 | ext_spi_clk |
| - | ^ AD1 | + | ^ AD1 |
| - | ^ AD2 | + | ^ AD2 |
| - | ^ ALS | + | ^ AD5 |
| - | ^ AMP2 | GPIO | + | ^ ALS |
| - | ^ BB | GPIO | + | ^ AMP2 | GPIO |
| - | ^ | + | ^ AQS |
| - | ^ BTN | + | ^ BB | GPIO |
| - | ^ CAN | + | ^ |
| - | ^ CLS | + | ^ BT2 |
| - | ^ CMPS2 | + | ^ BTN |
| - | ^ COLOR | + | ^ CAN |
| - | ^ DA1 | + | ^ CLS |
| - | ^ DHB1 | PWM/ | + | ^ CMPS2 |
| - | ^ DPG1 | SPI | 50 | ext_spi_clk | + | ^ COLOR |
| - | ^ ENC | + | ^ DA1 |
| - | ^ GPS | + | ^ DHB1 | PWM/ |
| - | ^ GYRO | SPI | 50 | ext_spi_clk | + | ^ DPG1 | SPI | 50 | ext_spi_clk |
| - | ^ HYGRO | + | ^ ENC |
| - | ^ JSTK | SPI | 16 | ext_spi_clk | + | ^ ESP32 |
| - | ^ JSTK2 | + | ^ GPS |
| - | ^ KYPD | GPIO | + | ^ GYRO | SPI | 50 | ext_spi_clk |
| - | ^ LED | + | ^ HYGRO |
| - | ^ MAXSONAR | + | ^ JSTK | SPI | 16 | ext_spi_clk |
| - | ^ MTDS | SPI | - | + | ^ JSTK2 |
| - | ^ NAV | + | ^ KYPD | GPIO |
| - | ^ OLED | SPI/ | + | ^ LED |
| - | ^ OLEDrgb | + | ^ MAXSONAR |
| - | ^ R2R | + | ^ MicroSD |
| - | ^ RTCC | IIC | - | + | ^ MTDS | SPI | - |
| - | ^ SD | SPI | - | + | ^ NAV |
| - | ^ SF3 | + | ^ OLED | SPI/ |
| - | ^ SSR | + | ^ OLEDrgb |
| - | ^ SWT | + | ^ PIR |
| - | ^ TC1 | + | ^ R2R |
| - | ^ TMP3 | IIC | - | + | ^ RTCC | IIC | - |
| - | ^ WIFI | SPI | - | + | ^ SD | SPI | - |
| + | ^ SF3 | ||
| + | ^ SSR | ||
| + | ^ SWT | ||
| + | ^ TC1 | ||
| + | ^ TMP3 | IIC | - | ||
| + | ^ WIFI | SPI | - | ||
| <-- | <-- | ||
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| === Hardware === | === Hardware === | ||
| - | * **A Supported Digilent 7-Series FPGA or Zynq Board** | + | * **Supported Digilent 7-Series FPGA System |
| - | * **USB Cables** | + | * **MicroUSB Cable/s** |
| * **One or More Supported Digilent Pmods** | * **One or More Supported Digilent Pmods** | ||
| === Software === | === Software === | ||
| - | * **Xilinx Vivado | + | * **Xilinx Vivado |
| - | * //Vivado 2015.4 is used in this tutorial// | + | |
| * //Other versions of Vivado may work, but functionality is not guaranteed// | * //Other versions of Vivado may work, but functionality is not guaranteed// | ||
| - | * **Xilinx SDK** | + | |
| - | | + | * **Digilent Vivado |
| - | * **Digilent Board Support Files** | + | * //[[# |
| - | * // | + | |
| - | * **Digilent Vivado Library | + | |
| - | * [[https://github.com/ | + | |
| - | * [[https:// | + | |
| - | * // | + | |
| ----- | ----- | ||
| <WRAP round important 660px> | <WRAP round important 660px> | ||
| - | ===Important.=== | + | ===Important=== |
| If the Pmod IP to be used has a README file, be sure to review it before starting this tutorial. This file can be found in the **vivado-library/ | If the Pmod IP to be used has a README file, be sure to review it before starting this tutorial. This file can be found in the **vivado-library/ | ||
| </ | </ | ||
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| ==== 1. Create a New Microblaze/ | ==== 1. Create a New Microblaze/ | ||
| - | >To determine whether you need to use Microblaze or Zynq for this tutorial, refer to the entry in the **Platforms Supported** dropdown table found in the [[# | + | >To determine whether you need to use Microblaze or Zynq for this tutorial, refer to the entry in the **Platforms Supported** dropdown table found in the [[# |
| --> Microblaze # | --> Microblaze # | ||
| - | >Follow the **"Getting Started with MicroBlaze" | + | >Follow the [[: |
| > | > | ||
| > | > | ||
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| --> Zynq # | --> Zynq # | ||
| - | >Follow the **"Getting Started with Zynq" | + | >Follow the [[: |
| > | > | ||
| > | > | ||
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| ====2. Add the Digilent Library Repository==== | ====2. Add the Digilent Library Repository==== | ||
| - | <WRAP round important 660px> | + | >2.1) Find the latest release of Digilent's [[https:// |
| - | ===Important=== | + | |
| - | If you haven't done so yet, download and extract | + | |
| - | </ | + | |
| - | >2.1) Click **Project Settings** under Project Manager. | + | >2.2) Click **Project Settings** under Project Manager. |
| > | > | ||
| > | > | ||
| - | >2.2) Click **IP** then open the **Repository Manager** tab. Click the {{: | + | >2.3) Click **IP** then open the **Repository Manager** tab. Click the {{: |
| > | > | ||
| > | > | ||
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| >8.2) The bit file generation will begin. The tool will run // | >8.2) The bit file generation will begin. The tool will run // | ||
| > | > | ||
| - | >This process can take anywhere from **5 to 60 minutes** depending on your computer and target | + | >This process can take anywhere from **5 to 60 minutes** depending on the computer |
| >8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click **Cancel**. | >8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click **Cancel**. | ||
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| ====9. Export the Hardware Design to SDK==== | ====9. Export the Hardware Design to SDK==== | ||
| - | > | + | > |
| > | > | ||
| > | > | ||
| > | > | ||
| - | >A new file directory will be created in your project directory under **echo_server.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace. | + | >A new file directory will be created in the project directory under **echo_server.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace. |
| - | >9.2) On the main toolbar, click **File** and then **Launch SDK**. Leave both of the dropdown menus as their default //Local to Project// and click **OK**. This will open Xilinx SDK and import | + | >9.2) On the main toolbar, click **File |
| > | > | ||
| > | > | ||
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| ----- | ----- | ||
| - | ====10. | + | ====10. Xilinx SDK==== |
| - | >The HW design specification and included IP blocks are displayed in the //system.hdf// file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, | + | >The HW design specification and included IP blocks are displayed in the "system.hdf" |
| > | > | ||
| > | > | ||
| - | >Within the //Project Explorer// tab on the left, you can see your hardware platform. | + | >Within the //Project Explorer// tab on the left, you can see the hardware platform |
| - | >The drivers for the Pmod IP device | + | >The drivers for any Pmod IPs in the design |
| ----- | ----- | ||
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| ----- | ----- | ||
| - | {{tag> | + | {{tag> |