Nexys 4 - Getting Started with Microblaze

This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator for the Nexys 4 FPGA board.

At the end of this tutorial you will have:

• Created a Microblaze based hardware ( HW ) design in Xilinx Vivado

• Created a .C Project in Xilinx Vivado SDK ( Software Development Kit) to display Hello World using the hardware design shown in the previous step

• Displayed the final output on both the SDK console and Tera Term

• Digilent Nexys 4 FPGA Board and Micro USB Cable for UART communication and JTAG programming

• Xilinx Vivado 2016.X with the SDK package.

• Board Support Files
  • These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks
  • Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards ) on how to install Board Support Files for Vivado

Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.

In addition to the Microblaze IP block, we would also like to make use of the DDR2 SDRAM component on the Nexys 4 DDR. Therefore a MIG ( Memory Interface Generator ) IP block will be added to our design.

Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Nexys 4 DDR.

I. Vivado

• Open Vivado and select Nexys 4 board
• Create an new Vivado Project
• Create empty block design workspace inside the new project
• Add required IP blocks using the IP integrator tool and build Hardware Design
• Validate and save block design
• Create HDL system wrapper
• Run design Synthesis and Implementation
• Generate Bit File
• Export Hardware Design including the generated bit stream file to SDK tool
• Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.

II. SDK

• Create new application project and select default Hello World template
• Program FPGA
• Run configuration by selecting the correct UART COM Port and Baud Rate

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1) Click on Create New Project. Choose the Project Name and Location such that there are no blank spaces. This is an important naming convention to follow for project names, file names and location paths. Underscore is a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects. Name your Project and select the Project location and click Next.

1.2) Choose Project Type as RTL Project. Leave the Do not specify sources box unchecked and click Next.

1.3) If you have followed the Board Support File Wiki guide then click next and select Boards. From the filter options make required selections for Vendor, Display Name and Board Revision. Nexys 4 should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.

1.4) A summary of the new project design sources and target device is displayed. Click Finish.

2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.

2.2) On the left you should see the Flow Navigator. Select Create Block Design under the IP Integrator. Give a name to your design without any empty spaces.

2.3) An empty design workspace is created where you can add IP blocks. Add an IP core by clicking on the Add IP icon. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for “Microblaze” and double click on it to add the IP block to your empty design.

3.1) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the Run Block Automation message prompt or by double clicking on the block itself.



3.2) Select Run Block Automation and a customization assistant window will open with default settings.

3.3) Change default settings in the block options as shown below and click OK. This will customize the block with our new user settings.

3.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. Do not click on Run Connection Automation yet.

4.1) Double click on the Clock Wizard (clk_wiz_1) IP block.

4.2) Choose sys clock for CLK_IN1.

4.3) Select the Output Clocks tab.

4.4) Set Reset Type as Active Low. The left panel shows a GUI representation of the block and its internal settings. Observe that the reset pin will now read as resetn. This graphically represents the internal setting for active low.

4.5) Now move to the Port Renaming tab. This will give you a summary of the inputs and outputs to the Clock Wizard IP block.Click OK to finish block automation of Clock Wizard. Do not select Run Connection Automation yet.

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5.1) Go to Add IP and search for “UART”.

5.2) Select the AXI Uartlite IP block.

5.3) This will add a UART block to the existing design. We need a UART controller to communicate between the terminal window on the Host-PC and the Nexys 4 DDR hardware.

6.1) Now select the Run Connection Automation from the Designer Assistance bar message prompt. This will open up the Run Connection Automation window. Select the ext_reset_in as shown. A description of the interface will be shown along with available signal options. Select reset as the board part interface.

6.2) Now select all available connections and click OK. Completing this step will connect all the IP blocks that have been added and customized up to this point. In addition to performing auto-connection of available IP blocks, a new IP block called microblaze_0_axi_periph will be added to our design. Two signal pins reset and sys_clock will be added as well. The pin signals point to the right indicating that they are inputs to the clock wizard block ( clk_wiz_1) and reset clock wizard block ( rst_clk_wiz_1_100M).

6.3) Now select the Run Connection Automation from the Designer Assistance bar message prompt.Now select all available connections and click OK.

6.4) Select the button circled in blue. This is the Regenerate Layout option that will re-arrange the IP blocks in the design.

7.1) Select Validate Design. This will check for design and connection errors.


7.2) After the design validation step we will proceed with creating a HDL System Wrapper.

13.1) As highlighted in this step, right click on design_1 and select Create HDL Wrapper. Let Vivado manage the wrapper and select OK.

13.2) A system wrapper file will be generated and a message will be displayed in the tcl console informing us that the wrapper.v file has been generated.