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--- learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:start [2016/11/15 00:49] – [1. Creating a New Project] jon peyron
+++ learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
 ====== Nexys 4 - Getting Started with Microblaze ======
+<WRAP round important 660px>
+=== Important! ===
+This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]].
+</WRAP>
 {{ :nexys:nexys4:overview1.png?300 |}}
@@ Line 102: / Line 108: @@
 >3.1) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the **Run Block Automation** message prompt or by double clicking on the block itself.
 >
->{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image2.jpg?500|}}
+>{{:vivado:mig_7.jpg?500|}}
+>
 >3.2) Select **Run Block Automation** and a customization assistant window will open with default settings.
 >
@@ Line 110: / Line 116: @@
 >3.3) Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings.
 >
->{{:nexys4-ddr:nexys4ddr-mb_blockauto.png?direct&500|}}
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image2.jpg?500|}}
 >3.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. **Do not click on Run Connection Automation yet.**
@@ Line 117: / Line 124: @@
 -----
+==== 4. Customization of Clock Wizard IP Block ====
+>4.1) Double click on the **Clock Wizard** (clk_wiz_1) IP block.
+>
+>{{:nexys4-ddr:nexys4ddr-clkwizard1.png?direct&500|}}
+>4.2) Choose **sys clock** for CLK_IN1.
+>
+>{{:nexys4-ddr:nexys4ddr-clkwizard2.png?direct&500|}}
+>4.3) Select the **Output Clocks** tab.
+>
+>{{:nexys4-ddr:nexys4ddr-clkwizard3.png?direct&500|}}
+>4.4) Set **Reset Type** as //Active Low//. The left panel shows a GUI representation of the block and its internal settings. Observe that the reset pin will now read as //resetn//. This graphically represents the internal setting for active low.
+>
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image3.jpg?500|}}
+>4.5) Now move to the **Port Renaming** tab. This will give you a summary of the inputs and outputs to the Clock Wizard IP block.Click **OK** to finish block automation of Clock Wizard. **Do not select Run Connection Automation yet**.
+>
+>
+-----
+==== 5. Adding UART IP Block ====
+>5.1)  Go to {{:genesys2:addip.jpg?nolink|}} **Add IP** and search for "UART".
+>
+>{{:vivado:mig_17.jpg?500|}}
+>5.2) Select the **AXI Uartlite** IP block.
+>
+>{{:vivado:mig_18.jpg?500|}}
+>5.3) This will add a UART block to the existing design. We need a UART controller to communicate between the terminal window on the Host-PC and the Nexys 4 hardware.
+>
+>{{:nexys4-ddr:nexys4ddr-adduart.png?direct&500|}}
+-----
+==== 6. Running Connection Automation for the First Time ====
+>6.1) Now select the **Run Connection Automation** from the //Designer Assistance// bar message prompt. This will open up the Run Connection Automation window. Select the **ext_reset_in** as shown. A description of the interface will be shown along with available signal options. Select **reset** as the board part interface.
+>
+>{{:vivado:mig_20.jpg?500|}}
+>6.2) Now select all available connections and click **OK**. Completing this step will connect all the IP blocks that have been added and customized up to this point. In addition to performing auto-connection of available IP blocks, a new IP block called **microblaze_0_axi_periph** will be added to our design. Two signal pins **reset** and **sys_clock** will be added as well. The pin signals point to the right indicating that they are inputs to the clock wizard block ( clk_wiz_1) and reset clock wizard block ( rst_clk_wiz_1_100M).
+>
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image4.jpg?500|}}
+>6.3) Now select the **Run Connection Automation** from the //Designer Assistance// bar message prompt.Now select all available connections and click **OK**.
+>
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image5.jpg?500|}}
+-----
+>6.4) Select the button circled in blue. This is the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** option that will re-arrange the IP blocks in the design.
+>
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image18.jpg?500|}}
+-----
+==== 7. Validate Design ====
+>7.1) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors.
+>
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image19.jpg?500|}}
+>
+>7.2) After the design validation step we will proceed with creating a HDL System Wrapper.
+>
+>
+-----
+==== 8. Creating HDL System Wrapper ====
+>8.1) As highlighted in this step, right click on //design_1// and select **Create HDL Wrapper**. Let Vivado manage the wrapper and select **OK**.
+>
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image6.jpg?500|}}
+>8.2) A system wrapper file will be generated and a message will be displayed in the tcl console informing us that the //wrapper.v// file has been generated.
+>
+>
+-----
+==== 9. Generating Bit File ====
+>9.1) In the //Flow Navigator// panel on the left, under //Program and Debug// select the //Generate Bitstream// option. If you haven't already saved your design, you will get a prompt to save the block design.
+>
+>
+>9.2) The bit file generation will begin. The tool will run //Synthesis// and //Implementation//. After both synthesis and implementation have been successfully completed, the actual bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.
+>
+>
+>9.3) After the bitstream has been generated, a message prompt may pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click on **Cancel**.
+>
+>{{:vivado:mig_42.jpg?500|}}
+-----
+==== 10. Exporting Hardware Design to SDK ====
+>10.1) On the top left corner of the window, from the tool bar click on //File// and select //Export Hardware//.
+>This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. **Make sure the generated bitstream is included by checking the box**.
+>
+>{{:vivado:mig_43.jpg?500|}}
+>10.2) A new file directory will be created under **Hello_World.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace.
+>If you browse to the location on the drive where the Vivado project has been created, you will see that new folders have been created under SDK. See TCL Console message in the screen capture below. Now that the design has been exported to Software Development Kit (SDK) tool, the next step will be to launch the SDK tool.
+>
+>{{:vivado:mig_44.jpg?500|}}
+-----
+==== 11. Launching SDK ====
+>11.1) Go to //File// and select //Launch SDK// and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete.
+>
+>{{:vivado:mig_45.jpg?500|}}
+-----
+==== 12. Creating New Application Project in SDK ====
+>12.1) Go to //File// in the main tool bar and select **New Application Project**. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure the //Target Hardware// is the correct hardware design. In our case, it will be **design_1_wrapper_hw_platform_0**.
+>If for example, you also have another hardware design in the //Project Explorer// window, then you will also see this design name in the Target Hardware drop down selection list.
+>Since we only have one hardware design  **design_1_wrapper_hw_platform_0** this will be our target hardware.  Select **Create New** under **Board Support Package**. The tool will automatically populate the **Board Support Package** name to match with the give project name.
+>Click Next.
+>
+>{{:vivado:mig_48.jpg?500|}}
+-----
+==== 13. Selecting Hello World Application from available templates ====
+>13.1) Select **Hello World** under //Available Templates// on the left panel and click Finish.
+>
+>{{:vivado:mig_49.jpg?500|}}
+>13.2) After completing the previous step, you will see two new folders in the //Project Explorer// panel:
+>
+>- **display_hello_world** which contains all the binaries, .C and .H (Header) files
+>- **display_hello_world_bsp** which is the board support folder
+>
+>**display_hello_world** is our main working source folder. This also contains an important file shown here which is the **lscript.ld**. This is a Xilinx auto generated linker script file. Double click on this file to open.
+>
+>{{:vivado:mig_50.jpg?500|}}
+-----
+==== 14. Programming FPGA with Bit File ====
+>14.1) Make sure that the Nexys 4 DDR is turned on and connected to the host PC with the provided micro USB cable.
+>In the quick selection tool bar, you will find a symbol with a red arrow and three green square boxes. This clickable button is physically located under the //Search// tab in the main tool bar.
+>Click on this symbol to open the Program FPGA window.
+>Make sure that the //Hardware Platform// is selected as **design_1_wrapper_hw_platform_0**.
+>In the software configuration box, under //ELF File to Initialize in Block RAM// column, the row option must read **bootloop**. If not, click on the row and select **bootloop**.
+>Now click on Program.
+>
+>{{:vivado:mig_53.jpg?500|}}
+-----
+==== 15. Run Configuration  ====
+>15.1) After the FPGA has been successfully programmed with the bit file, from the //Project Explorer// panel, right click on the **display_hello_world** project folder which has been highlighted in the screen capture below.
+>At the bottom of the drop down list, select **Run As** and then select **launch on hardware**.
+>{{:learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze:image15.jpg?500|}}
+}}
+-----
+==== 16. Using Terminal Emulator ====
+You can use any serial terminal you would like including the one on SDK. We use Tera Term.
+Refer to this link [[http://en.wikipedia.org/wiki/Tera_Term]] to know what Tera Term is.
+You can download and install Tera Term from this link [[http://ttssh2.sourceforge.jp/index.html.en]]
+>16.1) Establish a serial connection with the correct communication port inside Tera Term.
+>Go to //SDK Run Configurations// -> Apply and Run.
+>Tera Term will work as a Console by displaying the output.
+>Notice that inside the built-in console window of SDK, there is a message displayed that reads // Port COM4 is already in use// indicating that the //COM4// port is in use by Tera Term.
+>
+>{{:vivado:mig_61.jpg?500|}}
+-----
+/*{{tag>learn programmable-logic tutorial nexys-4 microblaze}}*/

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