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learn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze-servers:start [2016/07/08 21:14] – created Sam Klearn:programmable-logic:tutorials:nexys-4-getting-started-with-microblaze-servers:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-====== Getting Started with Microblaze Servers ======+====== Nexys 4 - Getting Started with Microblaze Servers ======
 {{ :nexys:nexys4:overview1.png?300 |}} {{ :nexys:nexys4:overview1.png?300 |}}
  
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 >3.2) Click "Run Block Automation" circled in blue, and change the options to match the ones in the picture below. Click "Ok". >3.2) Click "Run Block Automation" circled in blue, and change the options to match the ones in the picture below. Click "Ok".
 > >
->{{:nexys4-ddr:server_3.jpg?nolink&500|}}+>{{:nexys4-ddr:server_3.jpg?nolink&900|}}
  
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 >6.2) On the //AXI EthernetLite block//, connect the **MII output** to the **MII input** on the //Ethernet PHY MII to Reduced MII block//. To do this, hover over the blue rectangle next to MII+ until you see a pencil cursor. Click and drag this over to the +MII input of the other block and release. >6.2) On the //AXI EthernetLite block//, connect the **MII output** to the **MII input** on the //Ethernet PHY MII to Reduced MII block//. To do this, hover over the blue rectangle next to MII+ until you see a pencil cursor. Click and drag this over to the +MII input of the other block and release.
 > >
->{{:nexys:nexys4:4_update_pic2.jpg?direct500|}}+>{{:nexys:nexys4:4_update_pic2.jpg?direct700|}}
  
 >6.3) Click //"Run Connection Automation"//. Un-check the //microblaze_0// check-box and click OK. >6.3) Click //"Run Connection Automation"//. Un-check the //microblaze_0// check-box and click OK.
 > >
->{{:nexys:nexys4:3_update_pic3.jpg?direct500|}}+>{{:nexys:nexys4:3_update_pic3.jpg?direct700|}}
  
 >6.4) Click //Regenerate Layout// (circled in blue below), and your block design should look like this: >6.4) Click //Regenerate Layout// (circled in blue below), and your block design should look like this:
 > >
->{{:nexys4-ddr:server_12.jpg?nolink&500|}}+>{{:nexys4-ddr:server_12.jpg?nolink&700|}}
  
 >6.5)  >6.5) 
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 >  * Route **ip2intc_irpt** on the //AXI EthernetLite// block to **In1[0:0]** on the //Concat// block. >  * Route **ip2intc_irpt** on the //AXI EthernetLite// block to **In1[0:0]** on the //Concat// block.
 > >
->{{:nexys4-ddr:server_13.jpg?nolink&500|}}+>{{:nexys4-ddr:server_13.jpg?nolink&700|}}
 > >
 > >
 >  * Connect **resetn** on the //Clocking Wizard// block to the **reset** pin. >  * Connect **resetn** on the //Clocking Wizard// block to the **reset** pin.
 > >
->{{:nexys4-ddr:server_14.jpg?nolink&500|}}+>{{:nexys4-ddr:server_14.jpg?nolink&700|}}
  
 >6.6) Right click somewhere in the background (white space) of your design and click //Create Port...//, or use the shortcut, Ctrl-K. Name this port eth_ref_clk and change the options to the one in the picture below. >6.6) Right click somewhere in the background (white space) of your design and click //Create Port...//, or use the shortcut, Ctrl-K. Name this port eth_ref_clk and change the options to the one in the picture below.
 > >
->{{:nexys4-ddr:server_15.jpg?nolink&500|}}+>{{:nexys4-ddr:server_15.jpg?nolink&700|}}
  
 >6.7) Connect this **eth_ref_clk** pin to **ref_clk** on the //Ethernet PHY MII to Reducted MII// block. Then Connect both to the output pin clk_out2 from the clock wizard. >6.7) Connect this **eth_ref_clk** pin to **ref_clk** on the //Ethernet PHY MII to Reducted MII// block. Then Connect both to the output pin clk_out2 from the clock wizard.
 > >
->{{:nexys4-ddr:server_16.jpg?nolink&500|}}+>{{:nexys4-ddr:server_16.jpg?nolink&700|}}
  
  
 >6.8) Double click into the //AXI EMC block//, select Memory Bank1, settings are as seen below. >6.8) Double click into the //AXI EMC block//, select Memory Bank1, settings are as seen below.
 > >
->{{:nexys:nexys4:3_update_pic6.jpg?direct500|}}+>{{:nexys:nexys4:3_update_pic6.jpg?direct700|}}
  
 >6.9) click on the //Address Edditor// select both S_AXI_MEM and change the range to 16M. >6.9) click on the //Address Edditor// select both S_AXI_MEM and change the range to 16M.
 > >
->{{:nexys:nexys4:3_update_pic9.jpg?direct500|}}+>{{:nexys:nexys4:3_update_pic9.jpg?direct700|}}
  
  
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 >6.10) Clicking //Regenerate Layout// again will result in your final block design layout for this project. >6.10) Clicking //Regenerate Layout// again will result in your final block design layout for this project.
 > >
->{{:nexys:nexys4:3_update_pic8.jpg?direct500|}}+>{{:nexys:nexys4:3_update_pic8.jpg?direct700|}}
  
 >6.11) We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under the //Design// window, select the **Sources** tab. Expand the //contraints// folder, right click on //constr// and click "Add Sources..." >6.11) We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under the //Design// window, select the **Sources** tab. Expand the //contraints// folder, right click on //constr// and click "Add Sources..."
 > >
->{{:nexys4-ddr:server_19.jpg?nolink&500|}}+>{{:nexys4-ddr:server_19.jpg?nolink&700|}}
  
 >6.12) Select Add or create constraints and click Next. >6.12) Select Add or create constraints and click Next.
 > >
->{{:nexys4-ddr:server_20.jpg?nolink&500|}}+>{{:nexys4-ddr:server_20.jpg?nolink&700|}}
  
 >6.13) Click //Create File...//, name your new contraints file and click OK and then Finish. >6.13) Click //Create File...//, name your new contraints file and click OK and then Finish.
 > >
->{{:nexys4-ddr:server_21.jpg?nolink&500|}}+>{{:nexys4-ddr:server_21.jpg?nolink&700|}}
  
 >6.14) Open your new constraints file and paste the following line of code in it: >6.14) Open your new constraints file and paste the following line of code in it:
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 >6.15) Now, right click on your design_1 block diagram and click //"Create HDL Wrapper"//. When the window pops up, select the "Let Vivado manage wrapper and auto-update" bullet and click OK. >6.15) Now, right click on your design_1 block diagram and click //"Create HDL Wrapper"//. When the window pops up, select the "Let Vivado manage wrapper and auto-update" bullet and click OK.
 > >
->{{:nexys4-ddr:server_22.jpg?nolink&500|}}+>{{:nexys4-ddr:server_22.jpg?nolink&700|}}
  
 >6.16) Click "Generate Bitstream" at the top of the work space. This process will take a while. >6.16) Click "Generate Bitstream" at the top of the work space. This process will take a while.
 > >
->{{:nexys4-ddr:server_23.jpg?nolink&500|}}+>{{:nexys4-ddr:server_23.jpg?nolink&700|}}
  
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 >11.1) In the linker script, take a look at the **Available Memory Regions** box. The Name should be **axi_emc_0_s_AXI_MEMO_BASEADDR** and the Size should be 0x01000000  >11.1) In the linker script, take a look at the **Available Memory Regions** box. The Name should be **axi_emc_0_s_AXI_MEMO_BASEADDR** and the Size should be 0x01000000 
 > >
->{{:nexys:nexys4:4_update_pic1.jpg?direct&direct500|}}+>{{:nexys:nexys4:4_update_pic1.jpg?direct&direct900|}}
  
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-{{tag>learn programmable-logic tutorial nexsys-4 microblaze}}+{{tag>learn programmable-logic tutorial nexys-4 microblaze}}