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learn:programmable-logic:tutorials:htsspisf:start [2021/01/13 11:27] – Ana-Maria-Eliza Balaslearn:programmable-logic:tutorials:htsspisf:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board. This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board.
-You can follow the steps presented in the  [[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start#prerequisites|Microblaze tutorial]], and see below the missing steps for adding QSPI Flash and perform all the connections.+You can follow the steps presented in the  [[/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start#prerequisites|Microblaze tutorial]], and see below the missing steps for adding QSPI Flash and perform all the connections.
 Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present. Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present.
 === Hardware === === Hardware ===
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 ===Important if you are using a board with Macronix flash.=== ===Important if you are using a board with Macronix flash.===
-The source files that need editing are part of a library (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841939/xilisf) compiled into a bsp/domain. By navigating to the source files in SDK/Vitis, the local copy of the library's source files are opened. Any modification is done on this local copy and build into the static library (and application) upon build. However, when the source files of the bsp/domain are re-generated (context menu, Regenerate BSP sources), the changes are overwritten from the originals in the Xilinx install directory. Take care this does not happen.+The source files that need editing are part of a library (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841939/xilisf) compiled into a bsp/domain. By navigating to the source files in SDK/Vitis, the local copy of the library's source files are opened. Any modification is done on this local copy and build into the static library (and application) upon build. However, when the source files of the bsp/domain are re-generated (context menu, Regenerate BSP sources), the changes made as explained above are overwritten from the originals in the Xilinx install directory. Take care this does not happen.
  
 A more permanent solution is forking the library repository (https://github.com/Xilinx/embeddedsw) editing the sources there and including a path to the modified repository in SDK/Vitis Xilinx->Repositories->Global.  A more permanent solution is forking the library repository (https://github.com/Xilinx/embeddedsw) editing the sources there and including a path to the modified repository in SDK/Vitis Xilinx->Repositories->Global. 
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-Make sure to re-build the application after making these changes.+  * Make sure to re-build the application after making these changes.
  
 === 3. Program FPGA with bootloader === === 3. Program FPGA with bootloader ===