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learn:programmable-logic:tutorials:cmod-a7-getting-started-with-microblaze:start [2016/07/08 20:45] – created Sam Klearn:programmable-logic:tutorials:cmod-a7-getting-started-with-microblaze:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-====== Getting Started with Microblaze ======+====== Cmod A7 - Getting Started with Microblaze ====== 
 + 
 +<WRAP round important 660px> 
 +=== Important! === 
 +This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]]. 
 +</WRAP>
  
 {{:cmod_a7:gsmb13.jpg?nolink&500|}} {{:cmod_a7:gsmb13.jpg?nolink&500|}}
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 ===== Overview ===== ===== Overview =====
 ==== Description ==== ==== Description ====
-This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator for the Cmod A7 FPGA board. **NOTE: The Cmod A7 requires Vivado Design Edition or System Edition which supports the Kintex-7 FPGA** +This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator for the Cmod A7 FPGA board. 
  
-Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.  
  
-In addition to the Microblaze IP block, we would also like to make use of the DDR3 SDRAM component on the Cmod A7. Therefore a MIG ( Memory Interface Generator ) IP block will be added to our design. +Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.
  
-Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Cmod A7.+A UART ( universal asynchronous receiver/transmitter ) IP block will also be added to communicate between the host PC and the soft processor core running on the Cmod A7.
  
 ==== General Design Flow ==== ==== General Design Flow ====
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 === Software === === Software ===
-  * **Xilinx Vivado 2015.X** +  * **Xilinx Vivado 2015.X+** 
-    * //System Edition or Design Edition must be installed to support the Kintex-7 FPGA//+    * //Should work for 2016.X as well//
   * **Xilinx SDK**   * **Xilinx SDK**
     * //Same version as your vivado installation//     * //Same version as your vivado installation//
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 === Board Support Files === === Board Support Files ===
   * **Board Support Files** -- These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.    * **Board Support Files** -- These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks. 
-    * Follow this Wiki guide **[[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]** on how to install Board Support Files for Vivado 2015.X+    * Follow this Wiki guide **[[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]** on how to install Board Support Files for Vivado 2015.X+
  
  
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 >{{:genesys2:gsmb27.jpg?nolink&500|}} >{{:genesys2:gsmb27.jpg?nolink&500|}}
  
-{{tag>learn programmable-logic tutorial cmod-a7 microblaze}}+/*{{tag>learn programmable-logic tutorial cmod-a7 microblaze}}*/