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learn:programmable-logic:tutorials:basys-3-getting-started-with-microblaze:start [2016/07/14 23:37] – [5. Adding Peripheral Components] jon peyronlearn:programmable-logic:tutorials:basys-3-getting-started-with-microblaze:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-====== Basys 3 - Getting started in Microblaze  ======+====== Basys 3 Getting started in Microblaze  ====== 
 + 
 +<WRAP round important 660px> 
 +=== Important! === 
 +This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]]. 
 +</WRAP>
  
 >{{:basys3:abacus_multiply.jpg?600|}} >{{:basys3:abacus_multiply.jpg?600|}}
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 {{:basys3:image_8.1.jpg?600|}} {{:basys3:image_8.1.jpg?600|}}
  
->4.3) Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings.+>4.3) Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings.  
 +> 
 +>Local Memory: 128KB 
 +>Local Memory ECC: None 
 +>Cache Configuration: None 
 +>Debug Module: Debug only 
 +>Peripheral AXI Port: Enabled 
 +>Interrupt Controller: unchecked 
 +>Clock Connection: /clk_wiz0/clk_out1(100 MHZ)
 > >
 >{{:basys3:image_1.1.jpg?600|}} >{{:basys3:image_1.1.jpg?600|}}
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 >{{:basys3:image_12.1.jpg?600|}} >{{:basys3:image_12.1.jpg?600|}}
  
->5.4) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors. There will be an error with the reset of the clock wizard and the rst_clk_wiz.+>5.4) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors. 
 > >
->{{:basys3:image_10.jpg?600|}} 
- 
->5.5) Select messages and look at only the Errors. Click on the second blue link and change from active low to active high in the box above the messages console. 
 > >
->{{:basys3:image_13.1.jpg?600|}} +>5.5) Click the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** button to rearrange your block design. The block design should look like
-  +
->5.6) Add an IP core by clicking on the {{:genesys2:addip.jpg?nolink|}} **Add IP** icon. Search for "Processor System Reset" and double click on it to add the IP block to your design.+
 > >
->{{:basys3:image_11.jpg?600|}} +>{{:learn:programmable-logic:tutorials:basys-3-getting-started-with-microblaze:gsmb_basys3.jpg?800|}}
- +
->5.7) Move all the connections to and from the rst_clk_wiz to the Processor System Reset. Once all of the wires have been moved to the Processor System Reset remove the rst_clk_wiz from the design.   +
 > >
->{{:basys3:image_13.jpg?600|}} +>5.6) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors.
- +
-5.8) Click the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** button to rearrange your block design. The block design should look like +
-> +
->{{:basys3:image_19.1.jpg?600|}} +
- +
-5.9) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors.+
 > >
 >{{:basys3:image_14.1.jpg?600|}} >{{:basys3:image_14.1.jpg?600|}}
  
->5.10) Click into the Processor System Reset. Under the basic tab the Ext Reset Logic Level(auto) should be set to 1. 
-> 
->{{:basys3:image_16.jpg?600|}} 
 ----- -----
  
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 >12.2) Your program will run and you should see "Hello World" pop up inside of your Serial Terminal. Hooray! >12.2) Your program will run and you should see "Hello World" pop up inside of your Serial Terminal. Hooray!
 > >
->{{:basys3:image_28.jpg?600|}}+>{{:basys3:image_17.1.jpg?600|}} 
 ----- -----
 +/*{{tag>learn programmable-logic tutorial basys-3}}*/