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learn:programmable-logic:tutorials:basys-3-getting-started-with-microblaze:start [2016/07/14 19:54] – jon peyronlearn:programmable-logic:tutorials:basys-3-getting-started-with-microblaze:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-====== Basys 3 - Getting started in Microblaze  ======+====== Basys 3 Getting started in Microblaze  ====== 
 + 
 +<WRAP round important 660px> 
 +=== Important! === 
 +This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]]. 
 +</WRAP>
  
 >{{:basys3:abacus_multiply.jpg?600|}} >{{:basys3:abacus_multiply.jpg?600|}}
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 >{{:basys3:image_5.jpg?600|}} >{{:basys3:image_5.jpg?600|}}
  
->3.3) Double click the **Clocking Wizard** block to customize it. Click on the **Output Clocks** tab and confirm **clk_out1** to "100.000". Make sure the **Reset Type** to **Active high**+>3.3) Double click the **Clocking Wizard** block to customize it. Click on the **Output Clocks** tab. Make sure **clk_out1** is "100.000" and the **Reset Type** is **Active High**
 > >
 >{{:basys3:image_6.jpg?600|}} >{{:basys3:image_6.jpg?600|}}
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 {{:basys3:image_8.1.jpg?600|}} {{:basys3:image_8.1.jpg?600|}}
  
->4.3) Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings.+>4.3) Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings.  
 +> 
 +>Local Memory: 128KB 
 +>Local Memory ECC: None 
 +>Cache Configuration: None 
 +>Debug Module: Debug only 
 +>Peripheral AXI Port: Enabled 
 +>Interrupt Controller: unchecked 
 +>Clock Connection: /clk_wiz0/clk_out1(100 MHZ) 
 +> 
 +>{{:basys3:image_1.1.jpg?600|}}
 > >
->{{:basys3:image_7.jpg?600|}} 
- 
 >4.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. **Do not click on Run Connection Automation yet.** >4.4) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. **Do not click on Run Connection Automation yet.**
 > >
 +{{:basys3:image_9.1.jpg?600|}}
  
 +-----
 +
 +==== 5. Adding Peripheral Components ====
 +
 +>5.1) Go into the **Boards** tab again and find the **USB UART** component. **Click and drag** this onto the block design to add the Uartlite block to your design.
 +>
 +>:{{:basys3:image_10.1.jpg?600|}}
 +
 +>5.2) Click **Run Connection Automation** in the green banner. Check the **All Automation** box and then click **OK**.
 +>
 +>{{:basys3:image_11.1.jpg?600|}}
 +
 +>5.3) Click **Run Connection Automation** again in the green banner. Check the **All Automation** box and then click **OK**.
 +>
 +>{{:basys3:image_12.1.jpg?600|}}
 +
 +>5.4) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors. 
 +>
 +>
 +>5.5) Click the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** button to rearrange your block design. The block design should look like
 +>
 +>{{:learn:programmable-logic:tutorials:basys-3-getting-started-with-microblaze:gsmb_basys3.jpg?800|}}
 +>
 +>5.6) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors.
 +>
 +>{{:basys3:image_14.1.jpg?600|}}
 +
 +-----
 +
 +==== 6. Making an HDL Wrapper ====
 +
 +>6.1) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the **Sources** tab and find your block design.
 +>
 +>{{:genesys2:gsmb16.jpg?nolink&500|}}
 +>
 +>6.2) Right click on your block design and click **Create HDL Wrapper**. Make sure **Let Vivado manage wrapper and auto-update** is selected and click **OK**.
 +>
 +>{{:genesys2:gsmb17.jpg?nolink&500|}}
 +>
 +>This will create a top module in Verilog and will allow you to generate a bitstream.
 +
 +-----
 +==== 7. Generate a bitstream ====
 +
 +>7.1) Click Generate bitstream
 +>
 +>{{:basys3:image_15.1.jpg?600|}}
 +
 +
 +-----
 +====8. Exporting Hardware Design to SDK ====
 +
 +>8.1) On the main toolbar, click **File** and select **Export->Export Hardware**. Check the box to **Include Bitstream** and click **OK**. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. 
 +>
 +>{{:genesys2:gsmb18.jpg?nolink&400|}}
 +>
 +>A new file directory will be created under **Hello_World.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace. 
 +
 +>8.2) On the main toolbar, click **File** and then **Launch SDK**. Leave both of the dropdown menus as their default //Local to Project// and click **OK**. This will open Xilinx SDK and import your hardware.
 +>
 +>{{:genesys2:gsmb19.jpg?nolink&400|}}
 +
 +-----
 +
 +====9. Creating New Application Project in SDK ====
 +
 +>9.1) Click the {{:genesys2:new.jpg?nolink|}} **New** dropdown arrow and select **Xilinx->Application Project**.
 +>
 +>{{:genesys2:gsmb21.jpg?nolink&500|}}
 +>
 +>Give your project a name that has no empty spaces and click **Next**.
 +
 +>9.2) Select **Hello World** from the list of templates and click **Finish**.
 +>
 +>{{:genesys2:gsmb22.jpg?nolink&500|}}
 +
 +You will see two new folders in the **Project Explorer** panel. 
 +  * **Hello_world** which contains all the binaries, .C and .H (Header) files
 +  * **Hello_world_bsp** which is the board support folder 
 +
 +**Hello_world** is our main working source folder. This also contains an important file shown here which is the "lscript.ld". This is a Xilinx auto generated linker script file. Double click on this file to open.
 +
 +>9.3) Back in the **Project Explorer**, double click and open **helloworld.c** under the **src** folder.
 +>
 +>This is the main .C file which will print "Hello World" in the console when executed. 
 +>
 +>{{:basys3:image_24.jpg?600|}}
 +
 +====10. Programming FPGA with Bit File ====
 +
 +>10.1) Make sure that the Basys 3 is turned on and connected to the host PC via the USB-JTAG port - this port will serve dual purpose as the USB-UART connection to the Microblaze.
 +>
 +>On the top toolbar, click the {{:genesys2:programfpga.jpg?nolink|}} **Program FPGA** button.
 +
 +>10.2) Click **Program** to program your FPGA with your hardware design.
 +>
 +>{{:genesys2:gsmb24.jpg?nolink&500|}}
 +
 +-----
 +
 +====11. Setting up UART Terminal====
 +
 +>11.1) Open up a Serial Terminal application(Terra Term). Connect to the Basys 3 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.
 +>
 +>{{:genesys2:gsmb25.jpg?nolink&500|}}
 +>
 +>11.2) With Tera Term serial port settings
 +>
 +>{{:basys3:image_16.1.jpg?direct&300|}}
 +
 +-----
 +====12. Program the Microblaze Processor====
 +
 +>12.1) Back in SDK, select your **Hello_world** project and click the {{:genesys2:run.jpg?nolink|}} **Run As...** button. Select **Launch on Hardware (System Debugger)** and click **OK**.
 +>
 +>{{:genesys2:gsmb26.jpg?nolink&500|}}
 +
 +>12.2) Your program will run and you should see "Hello World" pop up inside of your Serial Terminal. Hooray!
 +>
 +>{{:basys3:image_17.1.jpg?600|}}
 +
 +-----
 +/*{{tag>learn programmable-logic tutorial basys-3}}*/