Differences
This shows you the differences between two versions of the page.
| learn:programmable-logic:tutorials:arty-z7-getting-started-with-zynq:start [2017/09/21 22:10] – [4. Run the Connection Automation Tool] jon peyron | learn:programmable-logic:tutorials:arty-z7-getting-started-with-zynq:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
|---|---|---|---|
| Line 1: | Line 1: | ||
| ====== Arty Z7 Getting started with Zynq ====== | ====== Arty Z7 Getting started with Zynq ====== | ||
| + | |||
| + | <WRAP round important 660px> | ||
| + | === Important! === | ||
| + | This guide is obsolete, the updated guide can be found [[: | ||
| + | </ | ||
| + | |||
| {{: | {{: | ||
| Line 9: | Line 15: | ||
| * Created a simple hardware design incorporating the on board LEDs, | * Created a simple hardware design incorporating the on board LEDs, | ||
| - | * Created a .C project in XIlinx Vivado SDK tieing | + | * Created a .C project in XIlinx Vivado SDK tying the on board LEDs and buttons together along with sending switch status through the USB-UART using the hardware design shown in the previous step. |
| ----- | ----- | ||
| Line 78: | Line 84: | ||
| > | > | ||
| - | >1.3) Enter a project | + | >1.3) Enter a Project |
| > | > | ||
| > | > | ||
| Line 119: | Line 125: | ||
| > | > | ||
| - | >3.2) Click the **Run Block Automation** link | + | >3.2) Click the **Run Block Automation** link and click **OK**. This will use the board files and correctly configure the ZYNQ processor for the Arty-Z7. |
| > | > | ||
| > | > | ||
| Line 132: | Line 138: | ||
| > | > | ||
| > | > | ||
| + | > | ||
| >3.5) Add another GPIO core by repeating step 3.3 but do not enable dual channel. | >3.5) Add another GPIO core by repeating step 3.3 but do not enable dual channel. | ||
| > | > | ||
| Line 160: | Line 167: | ||
| {{: | {{: | ||
| - | >4.6) Next let's clean up our Block Design. Click the {{: | + | >4.6) Next let's clean up our Block Design. Click the {{: |
| > | > | ||
| > | > | ||
| Line 168: | Line 175: | ||
| ==== 5. Generate HDL Wrapper and Validate Design ==== | ==== 5. Generate HDL Wrapper and Validate Design ==== | ||
| - | >5.1) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors. | + | >5.1) Select {{:learn:programmable-logic: |
| >5.2) After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the **Design Sources** tab, right-click on the block diagram file. We labeled it " | >5.2) After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the **Design Sources** tab, right-click on the block diagram file. We labeled it " | ||
| > | > | ||
| - | >{{:zybo:generate_hdl_wrapper.png?nolink& | + | >{{:learn:programmable-logic: |
| - | This will create a top module in VHDL and will allow you to generate a bitstream. | + | This will create a top module in VHDL or Verilog depending on what language you choose |
| ----- | ----- | ||
| Line 180: | Line 187: | ||
| ==== 6. Generate the Bitstream ==== | ==== 6. Generate the Bitstream ==== | ||
| - | >6.1) Click on **Generate Bitstream** at the bottom of the Flow Navigator. Wait for the process to complete and click OK. | + | >6.1) Click on **Generate Bitstream** at the bottom of the Flow Navigator. |
| > | > | ||
| - | >{{:zybo:generate_bitstream.png?nolink&400|}} | + | >{{:learn:programmable-logic: |
| + | > | ||
| + | >6.2) Next there are a series of popup boxes. On the first popup select save | ||
| + | > | ||
| + | > | ||
| + | > | ||
| + | >On the second popup select yes. You can choose to have this not notify you again. | ||
| + | > | ||
| + | > | ||
| + | > | ||
| + | >On the last popup choose the max number of jobs allowed if you have no other tasks going on your PC. Otherwise choose the number of jobs based on system needs. | ||
| + | > | ||
| + | > | ||
| + | > | ||
| ----- | ----- | ||
| Line 190: | Line 211: | ||
| >7.1) Go to file-> | >7.1) Go to file-> | ||
| > | > | ||
| - | >{{:zybo:export_hdwr.png?nolink& | + | >{{:learn:programmable-logic: |
| ----- | ----- | ||
| Line 198: | Line 219: | ||
| >8.1) Go to **File-> | >8.1) Go to **File-> | ||
| > | > | ||
| - | >{{:zybo:launch_sdk.png?nolink& | + | >{{:learn:programmable-logic: |
| ----- | ----- | ||
| Line 206: | Line 226: | ||
| >9.1) Go to **File-> | >9.1) Go to **File-> | ||
| > | > | ||
| - | >{{:zybo:sdk_new_app_project.png?nolink& | + | >{{:learn:programmable-logic: |
| - | >9.2) Enter the project details: | + | >9.2) Enter a Project name and leave the rest of the options on default settings. Then select |
| - | * Project name: " | + | > |
| - | | + | >{{:learn: |
| - | | + | |
| - | | + | |
| - | | + | |
| - | * Board Support Package: Create New (leave default name) | + | |
| - | {{:zybo:sdk_project_details.png?nolink& | + | |
| + | >9.3) Select the Hello World template. Then select **FINISH** | ||
| + | > | ||
| + | > | ||
| - | >9.3) The Hello World demo is a good starting point for this demo. Click **Next**, select **Hello World** and click **Finish**. This process will add two directories to the project explorer. | + | >9.4) Expand |
| - | + | ||
| - | >9.4) Expand **getting_started_with_ZYBO** | + | |
| > | > | ||
| - | >{{:zybo:open_hello_world_c.png?nolink& | + | >{{:learn:programmable-logic: |
| ----- | ----- | ||
| Line 296: | Line 312: | ||
| ==== 11. Run the Project ==== | ==== 11. Run the Project ==== | ||
| - | >11.1) Make sure that the Zybo is connected to the host PC via the **UART** USB Port and that JP5 is set to JTAG. To program the FPGA, on the top toolbar, click the {{: | + | >11.1) Make sure that the Arty-Z7 |
| - | > | + | > |
| >11.2) Save the project. | >11.2) Save the project. | ||
| - | >11.3) Right click the **getting_started_with_ZYBO** directory and select run as -> Launch on Hardware(System Debugger). | + | >11.3) Right click the **Getting_started_with_zynq** directory and select run as -> Launch on Hardware(System Debugger). |
| - | > | + | > |
| - | >11.4) The demo will be running on the ZYBO. Try playing around with the 4 switches | + | >11.4) The demo will be running on the Arty-Z7. Try playing around with the (labeled |
| >11.5) Tera Term or any serial terminal will work as a Console for displaying the output of the BTN's. | >11.5) Tera Term or any serial terminal will work as a Console for displaying the output of the BTN's. | ||
| Line 312: | Line 328: | ||
| > Set up the terminal as: | > Set up the terminal as: | ||
| - | > | + | > |
| + | |||
| + | >You should see something like this on the terminal depending on what you do with the switches. | ||
| + | >{{:learn: | ||
| ----- | ----- | ||
| - | {{tag> | + | /*{{tag> |