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learn:programmable-logic:tutorials:arty-pmod-vga-demo:start [2017/05/24 18:15] – Linked to updated github projects tutorial Arthur Brownlearn:programmable-logic:tutorials:arty-pmod-vga-demo:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ===Software=== ===Software===
-  * **Vivado Design Suite 2016.4** +  * **Vivado Design Suite 2016.X** 
     * //Newer versions can be used, but the procedure may vary slightly//     * //Newer versions can be used, but the procedure may vary slightly//
-  * **Digilent Board Support Files for Vivado**  
-    * Follow the [[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] guide on how to install Board Support Files for Vivado. 
  
  
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 ===== Downloads ===== ===== Downloads =====
  
-Arty Pmod VGA Project Repository -- [[https://github.com/Digilent/Arty-Pmod-VGA/releases/download/v2016.4-2/Arty-Pmod-VGA-2016.4-2.zip|ZIP]] [[https://github.com/Digilent/Arty-Pmod-VGA|GIT Repo]]+Arty Pmod VGA Project Repository -- [[https://github.com/Digilent/Arty-Pmod-VGA/releases/download/v2016.4-2/Arty-Pmod-VGA-2016.4-2.zip|ZIP Archive]] [[https://github.com/Digilent/Arty-Pmod-VGA|GIT Repo]]
  
 ------ ------
-===== How to...  ===== 
  
-==== 1. Program the Board ====+===== Download and Launch the Arty Pmod VGA Demo =====
  
->1.1) Follow the [[:learn:programmable-logic:tutorials:github-demos:start|Using Digilent Github Demos]] Tutorial. This is an HDL design project, and as such does not support Vivado SDK, select the tutoral options appropriate for a Vivado-only design.+>1) Follow the [[:learn:programmable-logic:tutorials:github-demos:start|Using Digilent Github Demo Projects]] Tutorial. This is an HDL design project, and as such does not support Vivado SDK, select the tutorial options appropriate for a Vivado-only design. Return to this guide when prompted to check for additional hardware requirements and setup.
  
->1.2) Once you have generated your bit file, make sure that you have your Pmod VGA plugged into your Arty's Pmod ports JB and JC. Use a VGA cable to connect the Pmod VGA to your monitor's VGA port. Return to the Github Projects Tutorial to finish programming your board.+>2) Once you have generated your bit file, make sure that you have your Pmod VGA plugged into your Arty's Pmod ports JB and JC. Use a VGA cable to connect the Pmod VGA to your monitor's VGA port. Return to the Github Projects Tutorial to finish programming your board.
  
-==== 2. Run the Project ====+===== Using the Arty Pmod VGA Demo =====
  
-This portion will help you run the demo and observe all its features.+==== 1. View Results ====
  
->2.1) View results 
-> 
 >The VGA monitor will display a set of colored, black, and white bars, along with a moving box, as shown below. You may need to adjust the settings of your monitor to properly align the demo image. >The VGA monitor will display a set of colored, black, and white bars, along with a moving box, as shown below. You may need to adjust the settings of your monitor to properly align the demo image.
 > >
 >{{:learn:programmable-logic:tutorials:arty-pmod-vga-demo:arty-pmod-vga-test-pattern.png?direct&500|}} >{{:learn:programmable-logic:tutorials:arty-pmod-vga-demo:arty-pmod-vga-test-pattern.png?direct&500|}}
  
->2.2) Changing the resolution +==== 2. Changing the resolution ==== 
->+
 >You may want to change the display resolution if your VGA monitor does not support 1080p, or you want to modify the demo for a specific application. >You may want to change the display resolution if your VGA monitor does not support 1080p, or you want to modify the demo for a specific application.
 > >
->To select a different display resolution, select the appropriate set of Sync Generation constants for your target resolution from the list starting at line 47 of **top.vhd**. Uncomment the ten corresponding constants, FRAME_WIDTH through V_POL, and comment out the default versions of those same constants. The default resolution is 1920x1080 @ 60Hz.+>To select a different display resolution, select the appropriate set of Sync Generation constants for your target resolution from the list starting at line 47 of **top.vhd**. Uncomment the ten corresponding constants, **FRAME_WIDTH** through **V_POL**, and comment the default versions of those same constants. The default resolution is 1920x1080 @ 60Hz.
 > >
 >Next select **Project Manager** in the Flow Navigator. In the **Hierarchy** tab of the Sources box, expand **top** under Design Sources and double click on **clk_div_inst**. Change the clk_out1 Requested frequency - circled in red below - to the required pxl_clk frequency specified in the selected resolution's Sync Generation comment block. Select **Ok**, then **Generate** in the Generate Output Products dialog that pops up. To reprogram your board with the new hardware, return to Step 2. >Next select **Project Manager** in the Flow Navigator. In the **Hierarchy** tab of the Sources box, expand **top** under Design Sources and double click on **clk_div_inst**. Change the clk_out1 Requested frequency - circled in red below - to the required pxl_clk frequency specified in the selected resolution's Sync Generation comment block. Select **Ok**, then **Generate** in the Generate Output Products dialog that pops up. To reprogram your board with the new hardware, return to Step 2.